********** Mapped Logic ********** |
RD_LED <= NOT (((i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7))
OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND data_out(6)))); |
WR_LED <= NOT (((NOT i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7))
OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND NOT data_out(6)))); |
FDCPE_data_out0: FDCPE port map (data_out(0),data_in(0),data_out_C(0),'0','0');
data_out_C(0) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
FDCPE_data_out1: FDCPE port map (data_out(1),data_in(1),data_out_C(1),'0','0');
data_out_C(1) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
FDCPE_data_out2: FDCPE port map (data_out(2),data_in(2),data_out_C(2),'0','0');
data_out_C(2) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
FDCPE_data_out3: FDCPE port map (data_out(3),data_in(3),data_out_C(3),'0','0');
data_out_C(3) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
FDCPE_data_out4: FDCPE port map (data_out(4),data_in(4),data_out_C(4),'0','0');
data_out_C(4) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
FDCPE_data_out5: FDCPE port map (data_out(5),data_in(5),data_out_C(5),'0','0');
data_out_C(5) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
FDCPE_data_out6: FDCPE port map (data_out(6),data_in(6),data_out_C(6),'0','0');
data_out_C(6) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
FDCPE_data_out7: FDCPE port map (data_out(7),data_in(7),data_out_C(7),'0','0');
data_out_C(7) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); |
o13_IRQA <= NOT i5_INTRQ; |
o15_DRQA <= NOT ((i4_ACK AND i8_INPACK AND data_out(7))); |
o17_IORD <= NOT (((i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7))
OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND data_out(6)))); |
o18_IOWR <= NOT (((NOT i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7))
OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND NOT data_out(6)))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |