cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: acsi_cf Date: 7-30-2020, 9:23PM Device Used: XC9536XL-10-VQ44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 14 /36 ( 39%) 26 /180 ( 14%) 26 /108 ( 24%) 8 /36 ( 22%) 29 /34 ( 85%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 7/18 13/54 12/90 15/17 FB2 7/18 13/54 14/90 14/17 ----- ----- ----- ----- 14/36 26/108 26/180 29/34 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 15 15 | I/O : 23 28 Output : 14 14 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 0 0 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 29 29 ** Power Data ** There are 14 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'acsi_cf.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'data_in<6>' based upon the LOC constraint 'P43'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'data_in<7>' based upon the LOC constraint 'P44'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'i1_A1' based upon the LOC constraint 'P1'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'i1_A1_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'data_in_7_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'data_in_6_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 14 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State RD_LED 2 7 FB1_6 2 I/O O STD FAST WR_LED 2 7 FB1_8 3 I/O O STD FAST o15_DRQA 1 3 FB1_10 6 I/O O STD FAST o13_IRQA 1 1 FB1_12 8 I/O O STD FAST data_out<5> 2 5 FB1_13 12 I/O O STD FAST RESET data_out<6> 2 5 FB1_14 13 I/O O STD FAST RESET data_out<7> 2 5 FB1_15 14 I/O O STD FAST RESET data_out<2> 2 5 FB2_6 33 GSR/I/O O STD FAST RESET data_out<3> 2 5 FB2_7 32 I/O O STD FAST RESET data_out<4> 2 5 FB2_9 30 I/O O STD FAST RESET o18_IOWR 2 7 FB2_11 28 I/O O STD FAST o17_IORD 2 7 FB2_12 27 I/O O STD FAST data_out<1> 2 5 FB2_13 23 I/O O STD FAST RESET data_out<0> 2 5 FB2_14 22 I/O O STD FAST RESET ** 15 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use i4_ACK FB1_1 40 I/O I data_in<4> FB1_2 41 I/O I data_in<6> FB1_3 43 GCK/I/O I data_in<5> FB1_4 42 I/O I data_in<7> FB1_5 44 GCK/I/O I i1_A1 FB1_7 1 GCK/I/O I i3_RW FB1_9 5 I/O I i2_CS FB1_11 7 I/O I data_in<3> FB2_1 39 I/O I data_in<2> FB2_2 38 I/O I data_in<1> FB2_3 36 GTS/I/O I i9_RESET FB2_4 37 I/O I data_in<0> FB2_5 34 GTS/I/O I i8_INPACK FB2_8 31 I/O I i5_INTRQ FB2_10 29 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 40 I/O I (unused) 0 0 0 5 FB1_2 41 I/O I (unused) 0 0 0 5 FB1_3 43 GCK/I/O I (unused) 0 0 0 5 FB1_4 42 I/O I (unused) 0 0 0 5 FB1_5 44 GCK/I/O I RD_LED 2 0 0 3 FB1_6 2 I/O O (unused) 0 0 0 5 FB1_7 1 GCK/I/O I WR_LED 2 0 0 3 FB1_8 3 I/O O (unused) 0 0 0 5 FB1_9 5 I/O I o15_DRQA 1 0 0 4 FB1_10 6 I/O O (unused) 0 0 0 5 FB1_11 7 I/O I o13_IRQA 1 0 0 4 FB1_12 8 I/O O data_out<5> 2 0 0 3 FB1_13 12 I/O O data_out<6> 2 0 0 3 FB1_14 13 I/O O data_out<7> 2 0 0 3 FB1_15 14 I/O O (unused) 0 0 0 5 FB1_16 16 I/O (unused) 0 0 0 5 FB1_17 18 I/O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: data_in<5> 6: data_out<7> 10: i4_ACK 2: data_in<6> 7: i1_A1 11: i5_INTRQ 3: data_in<7> 8: i2_CS 12: i8_INPACK 4: data_out<5> 9: i3_RW 13: i9_RESET 5: data_out<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RD_LED ...XXXXXXX.............................. 7 WR_LED ...XXXXXXX.............................. 7 o15_DRQA .....X...X.X............................ 3 o13_IRQA ..........X............................. 1 data_out<5> X.....XXX...X........................... 5 data_out<6> .X....XXX...X........................... 5 data_out<7> ..X...XXX...X........................... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 39 I/O I (unused) 0 0 0 5 FB2_2 38 I/O I (unused) 0 0 0 5 FB2_3 36 GTS/I/O I (unused) 0 0 0 5 FB2_4 37 I/O I (unused) 0 0 0 5 FB2_5 34 GTS/I/O I data_out<2> 2 0 0 3 FB2_6 33 GSR/I/O O data_out<3> 2 0 0 3 FB2_7 32 I/O O (unused) 0 0 0 5 FB2_8 31 I/O I data_out<4> 2 0 0 3 FB2_9 30 I/O O (unused) 0 0 0 5 FB2_10 29 I/O I o18_IOWR 2 0 0 3 FB2_11 28 I/O O o17_IORD 2 0 0 3 FB2_12 27 I/O O data_out<1> 2 0 0 3 FB2_13 23 I/O O data_out<0> 2 0 0 3 FB2_14 22 I/O O (unused) 0 0 0 5 FB2_15 21 I/O (unused) 0 0 0 5 FB2_16 20 I/O (unused) 0 0 0 5 FB2_17 19 I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: data_in<0> 6: data_out<5> 10: i2_CS 2: data_in<1> 7: data_out<6> 11: i3_RW 3: data_in<2> 8: data_out<7> 12: i4_ACK 4: data_in<3> 9: i1_A1 13: i9_RESET 5: data_in<4> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs data_out<2> ..X.....XXX.X........................... 5 data_out<3> ...X....XXX.X........................... 5 data_out<4> ....X...XXX.X........................... 5 o18_IOWR .....XXXXXXX............................ 7 o17_IORD .....XXXXXXX............................ 7 data_out<1> .X......XXX.X........................... 5 data_out<0> X.......XXX.X........................... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** RD_LED <= NOT (((i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7)) OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND data_out(6)))); WR_LED <= NOT (((NOT i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7)) OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND NOT data_out(6)))); FDCPE_data_out0: FDCPE port map (data_out(0),data_in(0),data_out_C(0),'0','0'); data_out_C(0) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); FDCPE_data_out1: FDCPE port map (data_out(1),data_in(1),data_out_C(1),'0','0'); data_out_C(1) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); FDCPE_data_out2: FDCPE port map (data_out(2),data_in(2),data_out_C(2),'0','0'); data_out_C(2) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); FDCPE_data_out3: FDCPE port map (data_out(3),data_in(3),data_out_C(3),'0','0'); data_out_C(3) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); FDCPE_data_out4: FDCPE port map (data_out(4),data_in(4),data_out_C(4),'0','0'); data_out_C(4) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); FDCPE_data_out5: FDCPE port map (data_out(5),data_in(5),data_out_C(5),'0','0'); data_out_C(5) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); FDCPE_data_out6: FDCPE port map (data_out(6),data_in(6),data_out_C(6),'0','0'); data_out_C(6) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); FDCPE_data_out7: FDCPE port map (data_out(7),data_in(7),data_out_C(7),'0','0'); data_out_C(7) <= (i9_RESET AND NOT i3_RW AND NOT i2_CS AND NOT i1_A1); o13_IRQA <= NOT i5_INTRQ; o15_DRQA <= NOT ((i4_ACK AND i8_INPACK AND data_out(7))); o17_IORD <= NOT (((i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7)) OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND data_out(6)))); o18_IOWR <= NOT (((NOT i3_RW AND NOT i2_CS AND i1_A1 AND data_out(7)) OR (NOT i4_ACK AND data_out(7) AND NOT data_out(5) AND NOT data_out(6)))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9536XL-10-VQ44 -------------------------------- /44 43 42 41 40 39 38 37 36 35 34 \ | 1 33 | | 2 32 | | 3 31 | | 4 30 | | 5 XC9536XL-10-VQ44 29 | | 6 28 | | 7 27 | | 8 26 | | 9 25 | | 10 24 | | 11 23 | \ 12 13 14 15 16 17 18 19 20 21 22 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 i1_A1 23 data_out<1> 2 RD_LED 24 TDO 3 WR_LED 25 GND 4 GND 26 VCC 5 i3_RW 27 o17_IORD 6 o15_DRQA 28 o18_IOWR 7 i2_CS 29 i5_INTRQ 8 o13_IRQA 30 data_out<4> 9 TDI 31 i8_INPACK 10 TMS 32 data_out<3> 11 TCK 33 data_out<2> 12 data_out<5> 34 data_in<0> 13 data_out<6> 35 VCC 14 data_out<7> 36 data_in<1> 15 VCC 37 i9_RESET 16 KPR 38 data_in<2> 17 GND 39 data_in<3> 18 KPR 40 i4_ACK 19 KPR 41 data_in<4> 20 KPR 42 data_in<5> 21 KPR 43 data_in<6> 22 data_out<0> 44 data_in<7> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536xl-10-VQ44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25