cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: Atari_Expansion Date: 3-13-2020, 9:53PM Device Used: XC9536XL-10-VQ44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 16 /36 ( 44%) 40 /180 ( 22%) 28 /108 ( 26%) 3 /36 ( 8%) 30 /34 ( 88%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 8/18 13/54 18/90 14/17 FB2 8/18 15/54 22/90 16/17 ----- ----- ----- ----- 16/36 28/108 40/180 30/34 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_IN' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 15 15 | I/O : 24 28 Output : 14 14 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 30 30 ** Power Data ** There are 16 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'Atari_Expansion.ise'. ************************* Summary of Mapped Logic ************************ ** 14 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State BAS_ENABLE 1 4 FB1_2 41 I/O O STD FAST EX_ADDR18 3 7 FB1_4 42 I/O O STD FAST DIV_CLK_IN 1 1 FB1_6 2 I/O O STD FAST RESET MAP_SELFTEST 1 4 FB1_8 3 I/O O STD FAST BASE_negOE 5 10 FB1_10 6 I/O O STD FAST BASE_negWE 5 10 FB1_12 8 I/O O STD FAST EX_ADDR19_TO_RAM1CSneg 1 5 FB1_14 13 I/O O STD FAST EX_ADDR19_TO_RAM2CS_neg 1 5 FB1_16 16 I/O O STD FAST EX_ADDR14 4 7 FB2_4 37 I/O O STD FAST EX_ADDR15 4 7 FB2_8 31 I/O O STD FAST EX_ADDR16 3 7 FB2_10 29 I/O O STD FAST EX_ADDR17 3 7 FB2_12 27 I/O O STD FAST EX_negOE 3 10 FB2_14 22 I/O O STD FAST EX_negWE 3 10 FB2_16 20 I/O O STD FAST ** 2 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State XLXN_401 0 0 FB2_17 STD RESET XLXN_332 2 2 FB2_18 STD RESET ** 16 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use PB1 FB1_1 40 I/O I CAS_INH FB1_3 43 GCK/I/O I PB6 FB1_5 44 GCK/I/O I CLK_IN FB1_7 1~ GCK/I/O GCK PB3 FB1_15 14 I/O I PB2 FB1_17 18 I/O I HALT FB2_1 39 I/O I R_W FB2_3 36 GTS/I/O I PHI2 FB2_5 34 GTS/I/O I PB5 FB2_6 33 GSR/I/O I PB4 FB2_7 32 I/O I A15 FB2_9 30 I/O I MEM_SEL FB2_11 28 I/O I PB7 FB2_13 23 I/O I EXTSEL FB2_15 21 I/O I A14 FB2_17 19 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 40 I/O I BAS_ENABLE 1 0 0 4 FB1_2 41 I/O O (unused) 0 0 0 5 FB1_3 43 GCK/I/O I EX_ADDR18 3 0 0 2 FB1_4 42 I/O O (unused) 0 0 0 5 FB1_5 44 GCK/I/O I DIV_CLK_IN 1 0 0 4 FB1_6 2 I/O O (unused) 0 0 0 5 FB1_7 1 GCK/I/O GCK MAP_SELFTEST 1 0 0 4 FB1_8 3 I/O O (unused) 0 0 0 5 FB1_9 5 I/O BASE_negOE 5 0 0 0 FB1_10 6 I/O O (unused) 0 0 0 5 FB1_11 7 I/O BASE_negWE 5 0 0 0 FB1_12 8 I/O O (unused) 0 0 0 5 FB1_13 12 I/O EX_ADDR19_TO_RAM1CSneg 1 0 0 4 FB1_14 13 I/O O (unused) 0 0 0 5 FB1_15 14 I/O I EX_ADDR19_TO_RAM2CS_neg 1 0 0 4 FB1_16 16 I/O O (unused) 0 0 0 5 FB1_17 18 I/O I (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: A14 6: PB1 10: PHI2 2: A15 7: PB4 11: R_W 3: CAS_INH 8: PB5 12: XLXN_332 4: EXTSEL 9: PB7 13: XLXN_401 5: MEM_SEL Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs BAS_ENABLE .....XXX.X.............................. 4 EX_ADDR18 XX..XXXX...X............................ 7 DIV_CLK_IN ............X........................... 1 MAP_SELFTEST ......XXXX.............................. 4 BASE_negOE XXXXX.XX.XXX............................ 10 BASE_negWE XXXXX.XX.XXX............................ 10 EX_ADDR19_TO_RAM1CSneg XX..X.XX................................ 5 EX_ADDR19_TO_RAM2CS_neg XX..X.XX................................ 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 39 I/O I (unused) 0 0 0 5 FB2_2 38 I/O (unused) 0 0 0 5 FB2_3 36 GTS/I/O I EX_ADDR14 4 0 0 1 FB2_4 37 I/O O (unused) 0 0 0 5 FB2_5 34 GTS/I/O I (unused) 0 0 0 5 FB2_6 33 GSR/I/O I (unused) 0 0 0 5 FB2_7 32 I/O I EX_ADDR15 4 0 0 1 FB2_8 31 I/O O (unused) 0 0 0 5 FB2_9 30 I/O I EX_ADDR16 3 0 0 2 FB2_10 29 I/O O (unused) 0 0 0 5 FB2_11 28 I/O I EX_ADDR17 3 0 0 2 FB2_12 27 I/O O (unused) 0 0 0 5 FB2_13 23 I/O I EX_negOE 3 0 0 2 FB2_14 22 I/O O (unused) 0 0 0 5 FB2_15 21 I/O I EX_negWE 3 0 0 2 FB2_16 20 I/O O XLXN_401 0 0 0 5 FB2_17 19 I/O I XLXN_332 2 0 0 3 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: A14 6: MEM_SEL 11: PB6 2: A15 7: PB2 12: PB7 3: CAS_INH 8: PB3 13: PHI2 4: EXTSEL 9: PB4 14: R_W 5: HALT 10: PB5 15: XLXN_332 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs EX_ADDR14 XX...XX.XX....X......................... 7 EX_ADDR15 XX...X.XXX....X......................... 7 EX_ADDR16 XX...X..XXX...X......................... 7 EX_ADDR17 XX...X..XX.X..X......................... 7 EX_negOE XXXX.X..XX..XXX......................... 10 EX_negWE XXXX.X..XX..XXX......................... 10 XLXN_401 ........................................ 0 XLXN_332 ....X.......X........................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** BASE_negOE <= NOT (((PHI2 AND EXTSEL AND CAS_INH AND A15 AND R_W) OR (PHI2 AND EXTSEL AND CAS_INH AND NOT A14 AND R_W) OR (MEM_SEL AND PB4 AND PHI2 AND EXTSEL AND CAS_INH AND R_W) OR (PB4 AND PHI2 AND EXTSEL AND CAS_INH AND XLXN_332 AND R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT XLXN_332 AND PB5 AND R_W))); BASE_negWE <= NOT (((PHI2 AND EXTSEL AND CAS_INH AND A15 AND NOT R_W) OR (PHI2 AND EXTSEL AND CAS_INH AND NOT A14 AND NOT R_W) OR (MEM_SEL AND PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT R_W) OR (PB4 AND PHI2 AND EXTSEL AND CAS_INH AND XLXN_332 AND NOT R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT XLXN_332 AND PB5 AND NOT R_W))); BAS_ENABLE <= NOT ((PB4 AND NOT PB1 AND PHI2 AND PB5)); FTCPE_DIV_CLK_IN: FTCPE port map (DIV_CLK_IN,'1',XLXN_401,'0','0'); EX_ADDR14 <= NOT (((NOT A14) OR (MEM_SEL AND NOT PB4 AND NOT A15 AND NOT PB2) OR (NOT PB4 AND NOT A15 AND XLXN_332 AND NOT PB2) OR (NOT MEM_SEL AND NOT A15 AND NOT XLXN_332 AND NOT PB5 AND NOT PB2))); EX_ADDR15 <= ((A15) OR (MEM_SEL AND NOT PB4 AND A14 AND PB3) OR (NOT PB4 AND A14 AND XLXN_332 AND PB3) OR (NOT MEM_SEL AND A14 AND NOT XLXN_332 AND NOT PB5 AND PB3)); EX_ADDR16 <= ((MEM_SEL AND NOT PB4 AND NOT A15 AND A14 AND PB6) OR (NOT PB4 AND NOT A15 AND A14 AND XLXN_332 AND PB6) OR (NOT MEM_SEL AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5 AND PB6)); EX_ADDR17 <= ((MEM_SEL AND NOT PB4 AND PB7 AND NOT A15 AND A14) OR (NOT PB4 AND PB7 AND NOT A15 AND A14 AND XLXN_332) OR (NOT MEM_SEL AND PB7 AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5)); EX_ADDR18 <= ((MEM_SEL AND NOT PB4 AND PB1 AND NOT A15 AND A14) OR (NOT PB4 AND PB1 AND NOT A15 AND A14 AND XLXN_332) OR (NOT MEM_SEL AND PB1 AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5)); EX_ADDR19_TO_RAM1CSneg <= NOT ((MEM_SEL AND NOT PB4 AND NOT A15 AND A14 AND PB5)); EX_ADDR19_TO_RAM2CS_neg <= (MEM_SEL AND NOT PB4 AND NOT A15 AND A14 AND PB5); EX_negOE <= NOT (((MEM_SEL AND NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND R_W) OR (NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND XLXN_332 AND R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5 AND R_W))); EX_negWE <= NOT (((MEM_SEL AND NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND NOT R_W) OR (NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND XLXN_332 AND NOT R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5 AND NOT R_W))); MAP_SELFTEST <= NOT ((PB4 AND NOT PB7 AND PHI2 AND PB5)); FDCPE_XLXN_332: FDCPE port map (XLXN_332,HALT,NOT PHI2,'0','0'); FTCPE_XLXN_401: FTCPE port map (XLXN_401,'1',CLK_IN,'0','0'); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9536XL-10-VQ44 -------------------------------- /44 43 42 41 40 39 38 37 36 35 34 \ | 1 33 | | 2 32 | | 3 31 | | 4 30 | | 5 XC9536XL-10-VQ44 29 | | 6 28 | | 7 27 | | 8 26 | | 9 25 | | 10 24 | | 11 23 | \ 12 13 14 15 16 17 18 19 20 21 22 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 CLK_IN 23 PB7 2 DIV_CLK_IN 24 TDO 3 MAP_SELFTEST 25 GND 4 GND 26 VCC 5 KPR 27 EX_ADDR17 6 BASE_negOE 28 MEM_SEL 7 KPR 29 EX_ADDR16 8 BASE_negWE 30 A15 9 TDI 31 EX_ADDR15 10 TMS 32 PB4 11 TCK 33 PB5 12 KPR 34 PHI2 13 EX_ADDR19_TO_RAM1CSneg 35 VCC 14 PB3 36 R_W 15 VCC 37 EX_ADDR14 16 EX_ADDR19_TO_RAM2CS_neg 38 KPR 17 GND 39 HALT 18 PB2 40 PB1 19 A14 41 BAS_ENABLE 20 EX_negWE 42 EX_ADDR18 21 EXTSEL 43 CAS_INH 22 EX_negOE 44 PB6 Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536xl-10-VQ44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25