Design Name | Atari_Expansion |
Device, Speed (SpeedFile Version) | XC9536XL, -10 (3.0) |
Date Created | Sun Feb 23 18:55:12 2020 |
Created By | Timing Report Generator: version P.20131013 |
Copyright | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
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Min. Clock Period | 14.000 ns. |
Max. Clock Frequency (fSYSTEM) | 71.429 MHz. |
Limited by Clock Pulse Width for PHI2 | |
Pad to Pad Delay (tPD) | 10.000 ns. |
Setup to Clock at the Pad (tSU) | 2.100 ns. |
Clock Pad to Output Pad Delay (tCO) | 17.900 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_P2P | 0.0 | 17.9 | 82 | 82 |
AUTO_TS_P2F | 0.0 | 8.3 | 2 | 2 |
AUTO_TS_F2P | 0.0 | 11.7 | 8 | 8 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
PHI2 to CS_RAMBASE | 0.000 | 17.900 | -17.900 |
PHI2 to EX_ADDR14 | 0.000 | 17.900 | -17.900 |
PHI2 to EX_ADDR15 | 0.000 | 17.900 | -17.900 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
HALT to XLXN_18.D | 0.000 | 8.300 | -8.300 |
PHI2 to XLXN_18.CLKF | 0.000 | 6.200 | -6.200 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
XLXN_18.Q to CS_RAMBASE | 0.000 | 11.700 | -11.700 |
XLXN_18.Q to EX_ADDR14 | 0.000 | 11.700 | -11.700 |
XLXN_18.Q to EX_ADDR15 | 0.000 | 11.700 | -11.700 |
Clock | fEXT (MHz) | Reason |
---|---|---|
PHI2 | 71.429 | Limited by Clock Pulse Width for PHI2 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
HALT | 2.100 | 1.400 |
Destination Pad | Clock (edge) to Pad |
---|---|
CS_RAMBASE | 17.900 |
EX_ADDR14 | 17.900 |
EX_ADDR15 | 17.900 |
EX_ADDR16 | 17.900 |
EX_ADDR17 | 17.900 |
EX_ADDR18 | 17.900 |
EX_negOE | 17.900 |
EX_negWE | 17.900 |
Source Pad | Destination Pad | Delay |
---|---|---|
A14 | CS_RAMBASE | 10.000 |
A14 | EX_ADDR14 | 10.000 |
A14 | EX_ADDR15 | 10.000 |
A14 | EX_ADDR16 | 10.000 |
A14 | EX_ADDR17 | 10.000 |
A14 | EX_ADDR18 | 10.000 |
A14 | EX_ADDR19_TO_RAM1CSneg | 10.000 |
A14 | EX_ADDR19_TO_RAM2CS_neg | 10.000 |
A14 | EX_negOE | 10.000 |
A14 | EX_negWE | 10.000 |
A15 | CS_RAMBASE | 10.000 |
A15 | EX_ADDR14 | 10.000 |
A15 | EX_ADDR15 | 10.000 |
A15 | EX_ADDR16 | 10.000 |
A15 | EX_ADDR17 | 10.000 |
A15 | EX_ADDR18 | 10.000 |
A15 | EX_ADDR19_TO_RAM1CSneg | 10.000 |
A15 | EX_ADDR19_TO_RAM2CS_neg | 10.000 |
A15 | EX_negOE | 10.000 |
A15 | EX_negWE | 10.000 |
CAS_INH | CS_RAMBASE | 10.000 |
CAS_INH | EX_negOE | 10.000 |
CAS_INH | EX_negWE | 10.000 |
MEM_SEL | CS_RAMBASE | 10.000 |
MEM_SEL | EX_ADDR14 | 10.000 |
MEM_SEL | EX_ADDR15 | 10.000 |
MEM_SEL | EX_ADDR16 | 10.000 |
MEM_SEL | EX_ADDR17 | 10.000 |
MEM_SEL | EX_ADDR18 | 10.000 |
MEM_SEL | EX_ADDR19_TO_RAM1CSneg | 10.000 |
MEM_SEL | EX_ADDR19_TO_RAM2CS_neg | 10.000 |
MEM_SEL | EX_negOE | 10.000 |
MEM_SEL | EX_negWE | 10.000 |
PB1 | BAS_ENABLE | 10.000 |
PB1 | EX_ADDR18 | 10.000 |
PB2 | EX_ADDR14 | 10.000 |
PB3 | EX_ADDR15 | 10.000 |
PB4 | BAS_ENABLE | 10.000 |
PB4 | CS_RAMBASE | 10.000 |
PB4 | EX_ADDR14 | 10.000 |
PB4 | EX_ADDR15 | 10.000 |
PB4 | EX_ADDR16 | 10.000 |
PB4 | EX_ADDR17 | 10.000 |
PB4 | EX_ADDR18 | 10.000 |
PB4 | EX_ADDR19_TO_RAM1CSneg | 10.000 |
PB4 | EX_ADDR19_TO_RAM2CS_neg | 10.000 |
PB4 | EX_negOE | 10.000 |
PB4 | EX_negWE | 10.000 |
PB4 | MAP_SELFTEST | 10.000 |
PB5 | BAS_ENABLE | 10.000 |
PB5 | CS_RAMBASE | 10.000 |
PB5 | EX_ADDR14 | 10.000 |
PB5 | EX_ADDR15 | 10.000 |
PB5 | EX_ADDR16 | 10.000 |
PB5 | EX_ADDR17 | 10.000 |
PB5 | EX_ADDR18 | 10.000 |
PB5 | EX_ADDR19_TO_RAM1CSneg | 10.000 |
PB5 | EX_ADDR19_TO_RAM2CS_neg | 10.000 |
PB5 | EX_negOE | 10.000 |
PB5 | EX_negWE | 10.000 |
PB5 | MAP_SELFTEST | 10.000 |
PB6 | EX_ADDR16 | 10.000 |
PB7 | EX_ADDR17 | 10.000 |
PB7 | MAP_SELFTEST | 10.000 |
PHI2 | BASE_negOE | 10.000 |
PHI2 | BASE_negWE | 10.000 |
PHI2 | BAS_ENABLE | 10.000 |
PHI2 | EX_negOE | 10.000 |
PHI2 | EX_negWE | 10.000 |
PHI2 | MAP_SELFTEST | 10.000 |
R_W | BASE_negOE | 10.000 |
R_W | BASE_negWE | 10.000 |
R_W | EX_negOE | 10.000 |
R_W | EX_negWE | 10.000 |