cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: ramcart Date: 5-15-2020, 9:50PM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 84 /144 ( 58%) 197 /720 ( 27%) 149/432 ( 34%) 27 /144 ( 19%) 75 /81 ( 93%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 15/18 23/54 30/90 11/11* FB2 4/18 23/54 12/90 10/10* FB3 10/18 23/54 22/90 7/10 FB4 0/18 0/54 0/90 10/10* FB5 9/18 11/54 17/90 9/10 FB6 11/18 23/54 30/90 8/10 FB7 17/18 23/54 38/90 10/10* FB8 18/18* 23/54 48/90 10/10* ----- ----- ----- ----- 84/144 149/432 197/720 75/81 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 19 19 | I/O : 67 73 Output : 40 40 | GCK/IO : 3 3 Bidirectional : 16 16 | GTS/IO : 4 4 GCK : 0 0 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 75 75 ** Power Data ** There are 84 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'ramcart.ise'. ************************* Summary of Mapped Logic ************************ ** 56 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State CAR_DTA_LOW<2> 2 4 FB1_2 11 I/O O STD FAST CAR_DTA_LOW<3> 2 4 FB1_3 12 I/O O STD FAST CAR_DTA_LOW<4> 2 4 FB1_5 13 I/O O STD FAST CAR_DTA_LOW<5> 2 4 FB1_6 14 I/O O STD FAST CAR_DTA_LOW<6> 2 4 FB1_8 15 I/O O STD FAST CAR_DTA_LOW<7> 2 4 FB1_9 16 I/O O STD FAST CAR_DTA_HIGH<0> 2 4 FB1_11 17 I/O O STD FAST CAR_DTA_HIGH<1> 2 4 FB1_12 18 I/O O STD FAST CAR_DTA_HIGH<2> 2 4 FB1_14 19 I/O O STD FAST CAR_DTA_HIGH<3> 2 4 FB1_15 20 I/O O STD FAST CAR_DTA_HIGH<4> 2 4 FB1_17 22 GCK/I/O O STD FAST CAR_DTA_LOW<0> 2 4 FB2_15 9 I/O O STD FAST CAR_DTA_LOW<1> 2 4 FB2_17 10 I/O O STD FAST CAR_DTA_HIGH<5> 2 4 FB3_2 23 GCK/I/O O STD FAST CAR_DTA_HIGH<6> 2 4 FB3_5 24 I/O O STD FAST CAR_DTA_HIGH<7> 2 4 FB3_6 25 I/O O STD FAST R_W_LED 1 2 FB3_8 27 GCK/I/O O STD FAST RAM_UP_LED 1 2 FB3_9 28 I/O O STD FAST RAM_LOW_LED 1 2 FB3_11 29 I/O O STD FAST TRIG_WE_OUT 1 2 FB3_15 33 I/O O STD FAST DTA_LOW_RAM<3> 2 4 FB5_2 35 I/O I/O STD FAST DTA_LOW_RAM<4> 2 4 FB5_5 36 I/O I/O STD FAST DTA_LOW_RAM<5> 2 4 FB5_6 37 I/O I/O STD FAST DTA_LOW_RAM<2> 2 4 FB5_8 39 I/O I/O STD FAST DTA_LOW_RAM<6> 2 4 FB5_9 40 I/O I/O STD FAST DTA_LOW_RAM<1> 2 4 FB5_11 41 I/O I/O STD FAST DTA_LOW_RAM<7> 2 4 FB5_12 42 I/O I/O STD FAST DTA_LOW_RAM<0> 2 4 FB5_14 43 I/O I/O STD FAST negCE1_RAM_LOWER 1 2 FB5_17 49 I/O O STD FAST RAM_A8 2 3 FB6_2 74 I/O O STD FAST RAM_A6 2 3 FB6_5 76 I/O O STD FAST RAM_A13 2 3 FB6_6 77 I/O O STD FAST RAM_A7 2 3 FB6_8 78 I/O O STD FAST RAM_A12 2 3 FB6_9 79 I/O O STD FAST RAM_A14 2 3 FB6_11 80 I/O O STD FAST RAM_A15 2 3 FB6_12 81 I/O O STD FAST OE_RAM_LOWER 2 4 FB7_2 50 I/O O STD FAST RESET DTA_UP_RAM<3> 2 4 FB7_5 52 I/O I/O STD FAST DTA_UP_RAM<4> 2 4 FB7_6 53 I/O I/O STD FAST DTA_UP_RAM<2> 2 4 FB7_8 54 I/O I/O STD FAST Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State DTA_UP_RAM<5> 2 4 FB7_9 55 I/O I/O STD FAST DTA_UP_RAM<1> 2 4 FB7_11 56 I/O I/O STD FAST DTA_UP_RAM<6> 2 4 FB7_12 58 I/O I/O STD FAST DTA_UP_RAM<0> 2 4 FB7_14 59 I/O I/O STD FAST DTA_UP_RAM<7> 2 4 FB7_15 60 I/O I/O STD FAST RAM_A0 2 3 FB7_17 61 I/O O STD FAST negCE1_RAM_UPPER 1 2 FB8_2 63 I/O O STD FAST RAM_A1 2 3 FB8_5 64 I/O O STD FAST RAM_A10 2 3 FB8_6 65 I/O O STD FAST RAM_A2 2 3 FB8_8 66 I/O O STD FAST OE_RAM_UPPER 2 4 FB8_9 67 I/O O STD FAST RESET RAM_A3 2 3 FB8_11 68 I/O O STD FAST RAM_A11 2 3 FB8_12 70 I/O O STD FAST RAM_A4 2 3 FB8_14 71 I/O O STD FAST RAM_A9 2 3 FB8_15 72 I/O O STD FAST RAM_A5 2 3 FB8_17 73 I/O O STD FAST ** 28 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State XLXI_203/Q<1> 2 2 FB1_10 STD RESET WR_GO 2 3 FB1_13 STD RESET RAM_LOWER_LED 2 3 FB1_16 STD RESET CODE_RST<2> 2 2 FB1_18 STD RESET adres<15> 4 19 FB2_16 STD RESET adres<14> 4 18 FB2_18 STD RESET adres<13> 4 17 FB3_16 STD RESET adres<12> 4 16 FB3_17 STD RESET adres<11> 4 15 FB3_18 STD RESET adres<9> 4 13 FB6_15 STD RESET adres<8> 4 12 FB6_16 STD RESET adres<7> 4 11 FB6_17 STD RESET adres<10> 4 14 FB6_18 STD RESET $OpTx$$OpTx$FX_DC$67_INV$100 1 2 FB7_3 STD XLXN_237 2 10 FB7_4 STD RESET XLXI_203/Q<0> 2 5 FB7_7 STD RESET XLXN_418 3 11 FB7_10 STD RESET XLXN_239 3 11 FB7_13 STD RESET XLXN_238 3 11 FB7_16 STD RESET $OpTx$FX_DC$76 4 6 FB7_18 STD XLXI_203/Q<1>/XLXI_203/Q<1>_RSTF 2 3 FB8_1 STD adres<0> 3 4 FB8_3 STD RESET adres<6> 4 10 FB8_4 STD RESET adres<5> 4 9 FB8_7 STD RESET adres<4> 4 8 FB8_10 STD RESET adres<3> 4 7 FB8_13 STD RESET adres<2> 4 6 FB8_16 STD RESET adres<1> 4 5 FB8_18 STD RESET ** 19 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CART_A6 FB2_2 99 GSR/I/O I CART_ADDR<2> FB2_5 1 GTS/I/O I CART_A7 FB2_6 2 GTS/I/O I CART_ADDR<1> FB2_8 3 GTS/I/O I CART_ADDR<0> FB2_9 4 GTS/I/O I CART_ADDR<6> FB2_11 6 I/O I CART_ADDR<5> FB2_12 7 I/O I CART_ADDR<7> FB2_14 8 I/O I UDS FB4_2 87 I/O I CART_A1 FB4_5 89 I/O I CART_ROM4 FB4_6 90 I/O I CART_A2 FB4_8 91 I/O I CART_ROM3 FB4_9 92 I/O I CART_A3 FB4_11 93 I/O I CART_ADDR<3> FB4_12 94 I/O I CART_A4 FB4_14 95 I/O I CART_A5 FB4_15 96 I/O I CART_ADDR<4> FB4_17 97 I/O I LDS FB6_17 86 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) CAR_DTA_LOW<2> 2 0 0 3 FB1_2 11 I/O O CAR_DTA_LOW<3> 2 0 0 3 FB1_3 12 I/O O (unused) 0 0 0 5 FB1_4 (b) CAR_DTA_LOW<4> 2 0 0 3 FB1_5 13 I/O O CAR_DTA_LOW<5> 2 0 0 3 FB1_6 14 I/O O (unused) 0 0 0 5 FB1_7 (b) CAR_DTA_LOW<6> 2 0 0 3 FB1_8 15 I/O O CAR_DTA_LOW<7> 2 0 0 3 FB1_9 16 I/O O XLXI_203/Q<1> 2 0 0 3 FB1_10 (b) (b) CAR_DTA_HIGH<0> 2 0 0 3 FB1_11 17 I/O O CAR_DTA_HIGH<1> 2 0 0 3 FB1_12 18 I/O O WR_GO 2 0 0 3 FB1_13 (b) (b) CAR_DTA_HIGH<2> 2 0 0 3 FB1_14 19 I/O O CAR_DTA_HIGH<3> 2 0 0 3 FB1_15 20 I/O O RAM_LOWER_LED 2 0 0 3 FB1_16 (b) (b) CAR_DTA_HIGH<4> 2 0 0 3 FB1_17 22 GCK/I/O O CODE_RST<2> 2 0 0 3 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$67_INV$100 9: DTA_UP_RAM<3>.PIN 17: LDS 2: CART_A1 10: DTA_UP_RAM<4>.PIN 18: OE_RAM_LOWER 3: CART_A2 11: DTA_LOW_RAM<2>.PIN 19: UDS 4: CART_A3 12: DTA_LOW_RAM<3>.PIN 20: XLXI_203/Q<0> 5: CART_ROM4 13: DTA_LOW_RAM<4>.PIN 21: XLXI_203/Q<1> 6: DTA_UP_RAM<0>.PIN 14: DTA_LOW_RAM<5>.PIN 22: XLXI_203/Q<1>/XLXI_203/Q<1>_RSTF 7: DTA_UP_RAM<1>.PIN 15: DTA_LOW_RAM<6>.PIN 23: XLXN_418 8: DTA_UP_RAM<2>.PIN 16: DTA_LOW_RAM<7>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs CAR_DTA_LOW<2> X.........X.....XX...................... 4 CAR_DTA_LOW<3> X..........X....XX...................... 4 CAR_DTA_LOW<4> X...........X...XX...................... 4 CAR_DTA_LOW<5> X............X..XX...................... 4 CAR_DTA_LOW<6> X.............X.XX...................... 4 CAR_DTA_LOW<7> X..............XXX...................... 4 XLXI_203/Q<1> ...................X.X.................. 2 CAR_DTA_HIGH<0> X....X...........XX..................... 4 CAR_DTA_HIGH<1> X.....X..........XX..................... 4 WR_GO ...XX.................X................. 3 CAR_DTA_HIGH<2> X......X.........XX..................... 4 CAR_DTA_HIGH<3> X.......X........XX..................... 4 RAM_LOWER_LED .XX.X................................... 3 CAR_DTA_HIGH<4> X........X.......XX..................... 4 CODE_RST<2> ....................XX.................. 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 99 GSR/I/O I (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 1 GTS/I/O I (unused) 0 0 0 5 FB2_6 2 GTS/I/O I (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 3 GTS/I/O I (unused) 0 0 0 5 FB2_9 4 GTS/I/O I (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 6 I/O I (unused) 0 0 0 5 FB2_12 7 I/O I (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 8 I/O I CAR_DTA_LOW<0> 2 0 0 3 FB2_15 9 I/O O adres<15> 4 0 0 1 FB2_16 (b) (b) CAR_DTA_LOW<1> 2 0 0 3 FB2_17 10 I/O O adres<14> 4 0 0 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$67_INV$100 9: adres<0> 17: adres<3> 2: CART_A7 10: adres<10> 18: adres<4> 3: CART_ROM3 11: adres<11> 19: adres<5> 4: CART_ROM4 12: adres<12> 20: adres<6> 5: DTA_LOW_RAM<0>.PIN 13: adres<13> 21: adres<7> 6: DTA_LOW_RAM<1>.PIN 14: adres<14> 22: adres<8> 7: LDS 15: adres<1> 23: adres<9> 8: OE_RAM_LOWER 16: adres<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs CAR_DTA_LOW<0> X...X.XX................................ 4 adres<15> .XXX...XXXXXXXXXXXXXXXX................. 19 CAR_DTA_LOW<1> X....XXX................................ 4 adres<14> .XXX...XXXXXX.XXXXXXXXX................. 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) CAR_DTA_HIGH<5> 2 0 0 3 FB3_2 23 GCK/I/O O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) CAR_DTA_HIGH<6> 2 0 0 3 FB3_5 24 I/O O CAR_DTA_HIGH<7> 2 0 0 3 FB3_6 25 I/O O (unused) 0 0 0 5 FB3_7 (b) R_W_LED 1 0 0 4 FB3_8 27 GCK/I/O O RAM_UP_LED 1 0 0 4 FB3_9 28 I/O O (unused) 0 0 0 5 FB3_10 (b) RAM_LOW_LED 1 0 0 4 FB3_11 29 I/O O (unused) 0 0 0 5 FB3_12 30 I/O (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 32 I/O TRIG_WE_OUT 1 0 0 4 FB3_15 33 I/O O adres<13> 4 0 0 1 FB3_16 (b) (b) adres<12> 4 0 0 1 FB3_17 34 I/O (b) adres<11> 4 0 0 1 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$$OpTx$FX_DC$67_INV$100 9: RAM_LOWER_LED 17: adres<3> 2: CART_A7 10: UDS 18: adres<4> 3: CART_ROM3 11: adres<0> 19: adres<5> 4: CART_ROM4 12: adres<10> 20: adres<6> 5: DTA_UP_RAM<5>.PIN 13: adres<11> 21: adres<7> 6: DTA_UP_RAM<6>.PIN 14: adres<12> 22: adres<8> 7: DTA_UP_RAM<7>.PIN 15: adres<1> 23: adres<9> 8: OE_RAM_LOWER 16: adres<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs CAR_DTA_HIGH<5> X...X..X.X.............................. 4 CAR_DTA_HIGH<6> X....X.X.X.............................. 4 CAR_DTA_HIGH<7> X.....XX.X.............................. 4 R_W_LED .......X.............X.................. 2 RAM_UP_LED .......XX............................... 2 RAM_LOW_LED .......XX............................... 2 TRIG_WE_OUT ..X....X................................ 2 adres<13> .XXX...X..XXXXXXXXXXXXX................. 17 adres<12> .XXX...X..XXX.XXXXXXXXX................. 16 adres<11> .XXX...X..XX..XXXXXXXXX................. 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 87 I/O I (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 89 I/O I (unused) 0 0 0 5 FB4_6 90 I/O I (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 91 I/O I (unused) 0 0 0 5 FB4_9 92 I/O I (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 93 I/O I (unused) 0 0 0 5 FB4_12 94 I/O I (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 95 I/O I (unused) 0 0 0 5 FB4_15 96 I/O I (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 97 I/O I (unused) 0 0 0 5 FB4_18 (b) *********************************** FB5 *********************************** Number of function block inputs used/remaining: 11/43 Number of signals used by logic mapping into function block: 11 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) DTA_LOW_RAM<3> 2 0 0 3 FB5_2 35 I/O I/O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) DTA_LOW_RAM<4> 2 0 0 3 FB5_5 36 I/O I/O DTA_LOW_RAM<5> 2 0 0 3 FB5_6 37 I/O I/O (unused) 0 0 0 5 FB5_7 (b) DTA_LOW_RAM<2> 2 0 0 3 FB5_8 39 I/O I/O DTA_LOW_RAM<6> 2 0 0 3 FB5_9 40 I/O I/O (unused) 0 0 0 5 FB5_10 (b) DTA_LOW_RAM<1> 2 0 0 3 FB5_11 41 I/O I/O DTA_LOW_RAM<7> 2 0 0 3 FB5_12 42 I/O I/O (unused) 0 0 0 5 FB5_13 (b) DTA_LOW_RAM<0> 2 0 0 3 FB5_14 43 I/O I/O (unused) 0 0 0 5 FB5_15 46 I/O (unused) 0 0 0 5 FB5_16 (b) negCE1_RAM_LOWER 1 0 0 4 FB5_17 49 I/O O (unused) 0 0 0 5 FB5_18 (b) Signals Used by Logic in Function Block 1: CART_ADDR<0> 5: CART_ADDR<4> 9: CART_ROM3 2: CART_ADDR<1> 6: CART_ADDR<5> 10: OE_RAM_LOWER 3: CART_ADDR<2> 7: CART_ADDR<6> 11: RAM_LOWER_LED 4: CART_ADDR<3> 8: CART_ADDR<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DTA_LOW_RAM<3> ...X....XXX............................. 4 DTA_LOW_RAM<4> ....X...XXX............................. 4 DTA_LOW_RAM<5> .....X..XXX............................. 4 DTA_LOW_RAM<2> ..X.....XXX............................. 4 DTA_LOW_RAM<6> ......X.XXX............................. 4 DTA_LOW_RAM<1> .X......XXX............................. 4 DTA_LOW_RAM<7> .......XXXX............................. 4 DTA_LOW_RAM<0> X.......XXX............................. 4 negCE1_RAM_LOWER .........XX............................. 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) RAM_A8 2 0 0 3 FB6_2 74 I/O O (unused) 0 0 0 5 FB6_3 (b) (unused) 0 0 0 5 FB6_4 (b) RAM_A6 2 0 0 3 FB6_5 76 I/O O RAM_A13 2 0 0 3 FB6_6 77 I/O O (unused) 0 0 0 5 FB6_7 (b) RAM_A7 2 0 0 3 FB6_8 78 I/O O RAM_A12 2 0 0 3 FB6_9 79 I/O O (unused) 0 0 0 5 FB6_10 (b) RAM_A14 2 0 0 3 FB6_11 80 I/O O RAM_A15 2 0 0 3 FB6_12 81 I/O O (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 82 I/O adres<9> 4 0 0 1 FB6_15 85 I/O (b) adres<8> 4 0 0 1 FB6_16 (b) (b) adres<7> 4 0 0 1 FB6_17 86 I/O I adres<10> 4 0 0 1 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: CART_A7 9: OE_RAM_LOWER 17: adres<3> 2: CART_ADDR<0> 10: adres<0> 18: adres<4> 3: CART_ADDR<1> 11: adres<12> 19: adres<5> 4: CART_ADDR<5> 12: adres<13> 20: adres<6> 5: CART_ADDR<6> 13: adres<14> 21: adres<7> 6: CART_ADDR<7> 14: adres<15> 22: adres<8> 7: CART_ROM3 15: adres<1> 23: adres<9> 8: CART_ROM4 16: adres<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RAM_A8 ..X.....X............X.................. 3 RAM_A6 X.......X..........X.................... 3 RAM_A13 ....X...X..X............................ 3 RAM_A7 .X......X...........X................... 3 RAM_A12 ...X....X.X............................. 3 RAM_A14 .....X..X...X........................... 3 RAM_A15 .......XX....X.......................... 3 adres<9> X.....XXXX....XXXXXXXX.................. 13 adres<8> X.....XXXX....XXXXXXX................... 12 adres<7> X.....XXXX....XXXXXX.................... 11 adres<10> X.....XXXX....XXXXXXXXX................. 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB7_1 (b) OE_RAM_LOWER 2 0 0 3 FB7_2 50 I/O O $OpTx$$OpTx$FX_DC$67_INV$100 1 0 0 4 FB7_3 (b) (b) XLXN_237 2 0 0 3 FB7_4 (b) (b) DTA_UP_RAM<3> 2 0 0 3 FB7_5 52 I/O I/O DTA_UP_RAM<4> 2 0 0 3 FB7_6 53 I/O I/O XLXI_203/Q<0> 2 0 0 3 FB7_7 (b) (b) DTA_UP_RAM<2> 2 0 0 3 FB7_8 54 I/O I/O DTA_UP_RAM<5> 2 0 0 3 FB7_9 55 I/O I/O XLXN_418 3 0 0 2 FB7_10 (b) (b) DTA_UP_RAM<1> 2 0 0 3 FB7_11 56 I/O I/O DTA_UP_RAM<6> 2 0 0 3 FB7_12 58 I/O I/O XLXN_239 3 0 0 2 FB7_13 (b) (b) DTA_UP_RAM<0> 2 0 0 3 FB7_14 59 I/O I/O DTA_UP_RAM<7> 2 0 0 3 FB7_15 60 I/O I/O XLXN_238 3 0 0 2 FB7_16 (b) (b) RAM_A0 2 0 0 3 FB7_17 61 I/O O $OpTx$FX_DC$76 4 0 0 1 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$76 9: CART_ADDR<4> 17: RAM_LOWER_LED 2: CART_A1 10: CART_ADDR<5> 18: WR_GO 3: CART_A3 11: CART_ADDR<6> 19: XLXI_203/Q<1>/XLXI_203/Q<1>_RSTF 4: CART_A4 12: CART_ADDR<7> 20: XLXN_237 5: CART_ADDR<0> 13: CART_ROM3 21: XLXN_238 6: CART_ADDR<1> 14: CART_ROM4 22: XLXN_239 7: CART_ADDR<2> 15: CODE_RST<2> 23: adres<0> 8: CART_ADDR<3> 16: OE_RAM_LOWER Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs OE_RAM_LOWER ..XX.........X...X...................... 4 $OpTx$$OpTx$FX_DC$67_INV$100 ............XX.......................... 2 XLXN_237 ....XXXXXXXX.XX......................... 10 DTA_UP_RAM<3> .......X....X..XX....................... 4 DTA_UP_RAM<4> ........X...X..XX....................... 4 XLXI_203/Q<0> X.........XX.X....X..................... 5 DTA_UP_RAM<2> ......X.....X..XX....................... 4 DTA_UP_RAM<5> .........X..X..XX....................... 4 XLXN_418 ....XXXXXXXX.XX......X.................. 11 DTA_UP_RAM<1> .....X......X..XX....................... 4 DTA_UP_RAM<6> ..........X.X..XX....................... 4 XLXN_239 ....XXXXXXXX.XX.....X................... 11 DTA_UP_RAM<0> ....X.......X..XX....................... 4 DTA_UP_RAM<7> ...........XX..XX....................... 4 XLXN_238 ....XXXXXXXX.XX....X.................... 11 RAM_A0 .X.............X......X................. 3 $OpTx$FX_DC$76 ....XXXXXX.............................. 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use XLXI_203/Q<1>/XLXI_203/Q<1>_RSTF 2 0 0 3 FB8_1 (b) (b) negCE1_RAM_UPPER 1 0 0 4 FB8_2 63 I/O O adres<0> 3 0 0 2 FB8_3 (b) (b) adres<6> 4 0 0 1 FB8_4 (b) (b) RAM_A1 2 0 0 3 FB8_5 64 I/O O RAM_A10 2 0 0 3 FB8_6 65 I/O O adres<5> 4 0 0 1 FB8_7 (b) (b) RAM_A2 2 0 0 3 FB8_8 66 I/O O OE_RAM_UPPER 2 0 0 3 FB8_9 67 I/O O adres<4> 4 0 0 1 FB8_10 (b) (b) RAM_A3 2 0 0 3 FB8_11 68 I/O O RAM_A11 2 0 0 3 FB8_12 70 I/O O adres<3> 4 0 0 1 FB8_13 (b) (b) RAM_A4 2 0 0 3 FB8_14 71 I/O O RAM_A9 2 0 0 3 FB8_15 72 I/O O adres<2> 4 0 0 1 FB8_16 (b) (b) RAM_A5 2 0 0 3 FB8_17 73 I/O O adres<1> 4 0 0 1 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: CART_A2 9: CART_ADDR<4> 17: adres<11> 2: CART_A3 10: CART_ROM3 18: adres<1> 3: CART_A4 11: CART_ROM4 19: adres<2> 4: CART_A5 12: OE_RAM_LOWER 20: adres<3> 5: CART_A6 13: RAM_LOWER_LED 21: adres<4> 6: CART_A7 14: WR_GO 22: adres<5> 7: CART_ADDR<2> 15: adres<0> 23: adres<9> 8: CART_ADDR<3> 16: adres<10> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs XLXI_203/Q<1>/XLXI_203/Q<1>_RSTF .X........X..X.......................... 3 negCE1_RAM_UPPER ...........XX........................... 2 adres<0> .....X...XXX............................ 4 adres<6> .....X...XXX..X..XXXXX.................. 10 RAM_A1 X..........X.....X...................... 3 RAM_A10 .......X...X...X........................ 3 adres<5> .....X...XXX..X..XXXX................... 9 RAM_A2 .X.........X......X..................... 3 OE_RAM_UPPER .XX.......X..X.......................... 4 adres<4> .....X...XXX..X..XXX.................... 8 RAM_A3 ..X........X.......X.................... 3 RAM_A11 ........X..X....X....................... 3 adres<3> .....X...XXX..X..XX..................... 7 RAM_A4 ...X.......X........X................... 3 RAM_A9 ......X....X..........X................. 3 adres<2> .....X...XXX..X..X...................... 6 RAM_A5 ....X......X.........X.................. 3 adres<1> .....X...XXX..X......................... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$$OpTx$FX_DC$67_INV$100 <= (CART_ROM3 AND CART_ROM4); $OpTx$FX_DC$76 <= ((CART_ADDR(3) AND CART_ADDR(2) AND CART_ADDR(1) AND CART_ADDR(0) AND NOT CART_ADDR(5) AND NOT CART_ADDR(4)) OR (CART_ADDR(3) AND NOT CART_ADDR(2) AND NOT CART_ADDR(1) AND CART_ADDR(0) AND CART_ADDR(5) AND NOT CART_ADDR(4)) OR (NOT CART_ADDR(3) AND CART_ADDR(2) AND NOT CART_ADDR(1) AND NOT CART_ADDR(0) AND CART_ADDR(5) AND CART_ADDR(4)) OR (NOT CART_ADDR(3) AND NOT CART_ADDR(2) AND CART_ADDR(1) AND NOT CART_ADDR(0) AND CART_ADDR(5) AND CART_ADDR(4))); CAR_DTA_HIGH_I(0) <= DTA_UP_RAM(0).PIN; CAR_DTA_HIGH(0) <= CAR_DTA_HIGH_I(0) when CAR_DTA_HIGH_OE(0) = '1' else 'Z'; CAR_DTA_HIGH_OE(0) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_HIGH_I(1) <= DTA_UP_RAM(1).PIN; CAR_DTA_HIGH(1) <= CAR_DTA_HIGH_I(1) when CAR_DTA_HIGH_OE(1) = '1' else 'Z'; CAR_DTA_HIGH_OE(1) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_HIGH_I(2) <= DTA_UP_RAM(2).PIN; CAR_DTA_HIGH(2) <= CAR_DTA_HIGH_I(2) when CAR_DTA_HIGH_OE(2) = '1' else 'Z'; CAR_DTA_HIGH_OE(2) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_HIGH_I(3) <= DTA_UP_RAM(3).PIN; CAR_DTA_HIGH(3) <= CAR_DTA_HIGH_I(3) when CAR_DTA_HIGH_OE(3) = '1' else 'Z'; CAR_DTA_HIGH_OE(3) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_HIGH_I(4) <= DTA_UP_RAM(4).PIN; CAR_DTA_HIGH(4) <= CAR_DTA_HIGH_I(4) when CAR_DTA_HIGH_OE(4) = '1' else 'Z'; CAR_DTA_HIGH_OE(4) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_HIGH_I(5) <= DTA_UP_RAM(5).PIN; CAR_DTA_HIGH(5) <= CAR_DTA_HIGH_I(5) when CAR_DTA_HIGH_OE(5) = '1' else 'Z'; CAR_DTA_HIGH_OE(5) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_HIGH_I(6) <= DTA_UP_RAM(6).PIN; CAR_DTA_HIGH(6) <= CAR_DTA_HIGH_I(6) when CAR_DTA_HIGH_OE(6) = '1' else 'Z'; CAR_DTA_HIGH_OE(6) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_HIGH_I(7) <= DTA_UP_RAM(7).PIN; CAR_DTA_HIGH(7) <= CAR_DTA_HIGH_I(7) when CAR_DTA_HIGH_OE(7) = '1' else 'Z'; CAR_DTA_HIGH_OE(7) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(0) <= DTA_LOW_RAM(0).PIN; CAR_DTA_LOW(0) <= CAR_DTA_LOW_I(0) when CAR_DTA_LOW_OE(0) = '1' else 'Z'; CAR_DTA_LOW_OE(0) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(1) <= DTA_LOW_RAM(1).PIN; CAR_DTA_LOW(1) <= CAR_DTA_LOW_I(1) when CAR_DTA_LOW_OE(1) = '1' else 'Z'; CAR_DTA_LOW_OE(1) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(2) <= DTA_LOW_RAM(2).PIN; CAR_DTA_LOW(2) <= CAR_DTA_LOW_I(2) when CAR_DTA_LOW_OE(2) = '1' else 'Z'; CAR_DTA_LOW_OE(2) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(3) <= DTA_LOW_RAM(3).PIN; CAR_DTA_LOW(3) <= CAR_DTA_LOW_I(3) when CAR_DTA_LOW_OE(3) = '1' else 'Z'; CAR_DTA_LOW_OE(3) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(4) <= DTA_LOW_RAM(4).PIN; CAR_DTA_LOW(4) <= CAR_DTA_LOW_I(4) when CAR_DTA_LOW_OE(4) = '1' else 'Z'; CAR_DTA_LOW_OE(4) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(5) <= DTA_LOW_RAM(5).PIN; CAR_DTA_LOW(5) <= CAR_DTA_LOW_I(5) when CAR_DTA_LOW_OE(5) = '1' else 'Z'; CAR_DTA_LOW_OE(5) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(6) <= DTA_LOW_RAM(6).PIN; CAR_DTA_LOW(6) <= CAR_DTA_LOW_I(6) when CAR_DTA_LOW_OE(6) = '1' else 'Z'; CAR_DTA_LOW_OE(6) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); CAR_DTA_LOW_I(7) <= DTA_LOW_RAM(7).PIN; CAR_DTA_LOW(7) <= CAR_DTA_LOW_I(7) when CAR_DTA_LOW_OE(7) = '1' else 'Z'; CAR_DTA_LOW_OE(7) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); FTCPE_CODE_RST2: FTCPE port map (CODE_RST(2),'1',NOT XLXI_203/Q(1),XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF,'0'); DTA_LOW_RAM_I(0) <= CART_ADDR(0); DTA_LOW_RAM(0) <= DTA_LOW_RAM_I(0) when DTA_LOW_RAM_OE(0) = '1' else 'Z'; DTA_LOW_RAM_OE(0) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_LOW_RAM_I(1) <= CART_ADDR(1); DTA_LOW_RAM(1) <= DTA_LOW_RAM_I(1) when DTA_LOW_RAM_OE(1) = '1' else 'Z'; DTA_LOW_RAM_OE(1) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_LOW_RAM_I(2) <= CART_ADDR(2); DTA_LOW_RAM(2) <= DTA_LOW_RAM_I(2) when DTA_LOW_RAM_OE(2) = '1' else 'Z'; DTA_LOW_RAM_OE(2) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_LOW_RAM_I(3) <= CART_ADDR(3); DTA_LOW_RAM(3) <= DTA_LOW_RAM_I(3) when DTA_LOW_RAM_OE(3) = '1' else 'Z'; DTA_LOW_RAM_OE(3) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_LOW_RAM_I(4) <= CART_ADDR(4); DTA_LOW_RAM(4) <= DTA_LOW_RAM_I(4) when DTA_LOW_RAM_OE(4) = '1' else 'Z'; DTA_LOW_RAM_OE(4) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_LOW_RAM_I(5) <= CART_ADDR(5); DTA_LOW_RAM(5) <= DTA_LOW_RAM_I(5) when DTA_LOW_RAM_OE(5) = '1' else 'Z'; DTA_LOW_RAM_OE(5) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_LOW_RAM_I(6) <= CART_ADDR(6); DTA_LOW_RAM(6) <= DTA_LOW_RAM_I(6) when DTA_LOW_RAM_OE(6) = '1' else 'Z'; DTA_LOW_RAM_OE(6) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_LOW_RAM_I(7) <= CART_ADDR(7); DTA_LOW_RAM(7) <= DTA_LOW_RAM_I(7) when DTA_LOW_RAM_OE(7) = '1' else 'Z'; DTA_LOW_RAM_OE(7) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(0) <= CART_ADDR(0); DTA_UP_RAM(0) <= DTA_UP_RAM_I(0) when DTA_UP_RAM_OE(0) = '1' else 'Z'; DTA_UP_RAM_OE(0) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(1) <= CART_ADDR(1); DTA_UP_RAM(1) <= DTA_UP_RAM_I(1) when DTA_UP_RAM_OE(1) = '1' else 'Z'; DTA_UP_RAM_OE(1) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(2) <= CART_ADDR(2); DTA_UP_RAM(2) <= DTA_UP_RAM_I(2) when DTA_UP_RAM_OE(2) = '1' else 'Z'; DTA_UP_RAM_OE(2) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(3) <= CART_ADDR(3); DTA_UP_RAM(3) <= DTA_UP_RAM_I(3) when DTA_UP_RAM_OE(3) = '1' else 'Z'; DTA_UP_RAM_OE(3) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(4) <= CART_ADDR(4); DTA_UP_RAM(4) <= DTA_UP_RAM_I(4) when DTA_UP_RAM_OE(4) = '1' else 'Z'; DTA_UP_RAM_OE(4) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(5) <= CART_ADDR(5); DTA_UP_RAM(5) <= DTA_UP_RAM_I(5) when DTA_UP_RAM_OE(5) = '1' else 'Z'; DTA_UP_RAM_OE(5) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(6) <= CART_ADDR(6); DTA_UP_RAM(6) <= DTA_UP_RAM_I(6) when DTA_UP_RAM_OE(6) = '1' else 'Z'; DTA_UP_RAM_OE(6) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); DTA_UP_RAM_I(7) <= CART_ADDR(7); DTA_UP_RAM(7) <= DTA_UP_RAM_I(7) when DTA_UP_RAM_OE(7) = '1' else 'Z'; DTA_UP_RAM_OE(7) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); FDCPE_OE_RAM_LOWER: FDCPE port map (OE_RAM_LOWER,'1',OE_RAM_LOWER_C,OE_RAM_LOWER_CLR,'0'); OE_RAM_LOWER_C <= (CART_A4 AND NOT CART_ROM4 AND WR_GO); OE_RAM_LOWER_CLR <= (NOT CART_ROM4 AND CART_A3); FDCPE_OE_RAM_UPPER: FDCPE port map (OE_RAM_UPPER,'1',OE_RAM_UPPER_C,OE_RAM_UPPER_CLR,'0'); OE_RAM_UPPER_C <= (CART_A4 AND NOT CART_ROM4 AND WR_GO); OE_RAM_UPPER_CLR <= (NOT CART_ROM4 AND CART_A3); RAM_A0 <= ((adres(0) AND OE_RAM_LOWER) OR (CART_A1 AND NOT OE_RAM_LOWER)); RAM_A1 <= ((adres(1) AND OE_RAM_LOWER) OR (CART_A2 AND NOT OE_RAM_LOWER)); RAM_A10 <= ((adres(10) AND OE_RAM_LOWER) OR (CART_ADDR(3) AND NOT OE_RAM_LOWER)); RAM_A11 <= ((adres(11) AND OE_RAM_LOWER) OR (CART_ADDR(4) AND NOT OE_RAM_LOWER)); RAM_A12 <= ((adres(12) AND OE_RAM_LOWER) OR (CART_ADDR(5) AND NOT OE_RAM_LOWER)); RAM_A13 <= ((adres(13) AND OE_RAM_LOWER) OR (CART_ADDR(6) AND NOT OE_RAM_LOWER)); RAM_A14 <= ((adres(14) AND OE_RAM_LOWER) OR (CART_ADDR(7) AND NOT OE_RAM_LOWER)); RAM_A15 <= ((adres(15) AND OE_RAM_LOWER) OR (CART_ROM4 AND NOT OE_RAM_LOWER)); RAM_A2 <= ((adres(2) AND OE_RAM_LOWER) OR (CART_A3 AND NOT OE_RAM_LOWER)); RAM_A3 <= ((adres(3) AND OE_RAM_LOWER) OR (CART_A4 AND NOT OE_RAM_LOWER)); RAM_A4 <= ((adres(4) AND OE_RAM_LOWER) OR (CART_A5 AND NOT OE_RAM_LOWER)); RAM_A5 <= ((adres(5) AND OE_RAM_LOWER) OR (CART_A6 AND NOT OE_RAM_LOWER)); RAM_A6 <= ((adres(6) AND OE_RAM_LOWER) OR (CART_A7 AND NOT OE_RAM_LOWER)); RAM_A7 <= ((adres(7) AND OE_RAM_LOWER) OR (CART_ADDR(0) AND NOT OE_RAM_LOWER)); RAM_A8 <= ((adres(8) AND OE_RAM_LOWER) OR (CART_ADDR(1) AND NOT OE_RAM_LOWER)); RAM_A9 <= ((adres(9) AND OE_RAM_LOWER) OR (CART_ADDR(2) AND NOT OE_RAM_LOWER)); FDCPE_RAM_LOWER_LED: FDCPE port map (RAM_LOWER_LED,'1',RAM_LOWER_LED_C,RAM_LOWER_LED_CLR,'0'); RAM_LOWER_LED_C <= (NOT CART_ROM4 AND CART_A2); RAM_LOWER_LED_CLR <= (NOT CART_ROM4 AND CART_A1); RAM_LOW_LED <= NOT ((NOT RAM_LOWER_LED AND OE_RAM_LOWER)); RAM_UP_LED <= NOT ((RAM_LOWER_LED AND OE_RAM_LOWER)); R_W_LED <= NOT ((NOT adres(8) AND OE_RAM_LOWER)); TRIG_WE_OUT <= (NOT CART_ROM3 AND OE_RAM_LOWER); FDCPE_WR_GO: FDCPE port map (WR_GO,'1',XLXN_418,WR_GO_CLR,'0'); WR_GO_CLR <= (NOT CART_ROM4 AND CART_A3); FTCPE_XLXI_203/Q0: FTCPE port map (XLXI_203/Q(0),'1',XLXI_203/Q_C(0),XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF,'0'); XLXI_203/Q_C(0) <= (NOT CART_ADDR(7) AND CART_ADDR(6) AND NOT CART_ROM4 AND $OpTx$FX_DC$76); FTCPE_XLXI_203/Q1: FTCPE port map (XLXI_203/Q(1),'1',NOT XLXI_203/Q(0),XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF,'0'); XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF <= ((WR_GO) OR (NOT CART_ROM4 AND CART_A3)); FDCPE_XLXN_237: FDCPE port map (XLXN_237,'1',XLXN_237_C,CODE_RST(2),'0'); XLXN_237_C <= (NOT CART_ADDR(3) AND CART_ADDR(2) AND NOT CART_ADDR(1) AND NOT CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND CART_ADDR(5) AND CART_ADDR(4) AND NOT CART_ROM4); FDCPE_XLXN_238: FDCPE port map (XLXN_238,XLXN_237,XLXN_238_C,CODE_RST(2),'0'); XLXN_238_C <= (CART_ADDR(3) AND CART_ADDR(2) AND CART_ADDR(1) AND CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND NOT CART_ADDR(5) AND NOT CART_ADDR(4) AND NOT CART_ROM4); FDCPE_XLXN_239: FDCPE port map (XLXN_239,XLXN_238,XLXN_239_C,CODE_RST(2),'0'); XLXN_239_C <= (NOT CART_ADDR(3) AND NOT CART_ADDR(2) AND CART_ADDR(1) AND NOT CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND CART_ADDR(5) AND CART_ADDR(4) AND NOT CART_ROM4); FDCPE_XLXN_418: FDCPE port map (XLXN_418,XLXN_239,XLXN_418_C,CODE_RST(2),'0'); XLXN_418_C <= (CART_ADDR(3) AND NOT CART_ADDR(2) AND NOT CART_ADDR(1) AND CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND CART_ADDR(5) AND NOT CART_ADDR(4) AND NOT CART_ROM4); FTCPE_adres0: FTCPE port map (adres(0),'1',adres_C(0),adres_CLR(0),'0',OE_RAM_LOWER); adres_C(0) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(0) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres1: FTCPE port map (adres(1),adres(0),adres_C(1),adres_CLR(1),'0',OE_RAM_LOWER); adres_C(1) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(1) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres2: FTCPE port map (adres(2),adres_T(2),adres_C(2),adres_CLR(2),'0',OE_RAM_LOWER); adres_T(2) <= (adres(0) AND adres(1)); adres_C(2) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(2) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres3: FTCPE port map (adres(3),adres_T(3),adres_C(3),adres_CLR(3),'0',OE_RAM_LOWER); adres_T(3) <= (adres(0) AND adres(1) AND adres(2)); adres_C(3) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(3) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres4: FTCPE port map (adres(4),adres_T(4),adres_C(4),adres_CLR(4),'0',OE_RAM_LOWER); adres_T(4) <= (adres(0) AND adres(1) AND adres(2) AND adres(3)); adres_C(4) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(4) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres5: FTCPE port map (adres(5),adres_T(5),adres_C(5),adres_CLR(5),'0',OE_RAM_LOWER); adres_T(5) <= (adres(0) AND adres(4) AND adres(1) AND adres(2) AND adres(3)); adres_C(5) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(5) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres6: FTCPE port map (adres(6),adres_T(6),adres_C(6),adres_CLR(6),'0',OE_RAM_LOWER); adres_T(6) <= (adres(0) AND adres(4) AND adres(1) AND adres(5) AND adres(2) AND adres(3)); adres_C(6) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(6) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres7: FTCPE port map (adres(7),adres_T(7),adres_C(7),adres_CLR(7),'0',OE_RAM_LOWER); adres_T(7) <= (adres(0) AND adres(4) AND adres(1) AND adres(5) AND adres(2) AND adres(6) AND adres(3)); adres_C(7) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(7) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres8: FTCPE port map (adres(8),adres_T(8),adres_C(8),adres_CLR(8),'0',OE_RAM_LOWER); adres_T(8) <= (adres(0) AND adres(4) AND adres(1) AND adres(5) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(8) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(8) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres9: FTCPE port map (adres(9),adres_T(9),adres_C(9),adres_CLR(9),'0',OE_RAM_LOWER); adres_T(9) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(9) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(9) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres10: FTCPE port map (adres(10),adres_T(10),adres_C(10),adres_CLR(10),'0',OE_RAM_LOWER); adres_T(10) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(9) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(10) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(10) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres11: FTCPE port map (adres(11),adres_T(11),adres_C(11),adres_CLR(11),'0',OE_RAM_LOWER); adres_T(11) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(11) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(11) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres12: FTCPE port map (adres(12),adres_T(12),adres_C(12),adres_CLR(12),'0',OE_RAM_LOWER); adres_T(12) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(2) AND adres(6) AND adres(11) AND adres(3) AND adres(7)); adres_C(12) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(12) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres13: FTCPE port map (adres(13),adres_T(13),adres_C(13),adres_CLR(13),'0',OE_RAM_LOWER); adres_T(13) <= (adres(0) AND adres(4) AND adres(8) AND adres(12) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(2) AND adres(6) AND adres(11) AND adres(3) AND adres(7)); adres_C(13) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(13) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres14: FTCPE port map (adres(14),adres_T(14),adres_C(14),adres_CLR(14),'0',OE_RAM_LOWER); adres_T(14) <= (adres(0) AND adres(4) AND adres(8) AND adres(12) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(13) AND adres(2) AND adres(6) AND adres(11) AND adres(3) AND adres(7)); adres_C(14) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(14) <= (NOT CART_ROM4 AND CART_A7); FTCPE_adres15: FTCPE port map (adres(15),adres_T(15),adres_C(15),adres_CLR(15),'0',OE_RAM_LOWER); adres_T(15) <= (adres(0) AND adres(4) AND adres(8) AND adres(12) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(13) AND adres(2) AND adres(6) AND adres(11) AND adres(14) AND adres(3) AND adres(7)); adres_C(15) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(15) <= (NOT CART_ROM4 AND CART_A7); negCE1_RAM_LOWER <= (RAM_LOWER_LED AND OE_RAM_LOWER); negCE1_RAM_UPPER <= (NOT RAM_LOWER_LED AND OE_RAM_LOWER); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 CART_ADDR<2> 51 VCC 2 CART_A7 52 DTA_UP_RAM<3> 3 CART_ADDR<1> 53 DTA_UP_RAM<4> 4 CART_ADDR<0> 54 DTA_UP_RAM<2> 5 VCC 55 DTA_UP_RAM<5> 6 CART_ADDR<6> 56 DTA_UP_RAM<1> 7 CART_ADDR<5> 57 VCC 8 CART_ADDR<7> 58 DTA_UP_RAM<6> 9 CAR_DTA_LOW<0> 59 DTA_UP_RAM<0> 10 CAR_DTA_LOW<1> 60 DTA_UP_RAM<7> 11 CAR_DTA_LOW<2> 61 RAM_A0 12 CAR_DTA_LOW<3> 62 GND 13 CAR_DTA_LOW<4> 63 negCE1_RAM_UPPER 14 CAR_DTA_LOW<5> 64 RAM_A1 15 CAR_DTA_LOW<6> 65 RAM_A10 16 CAR_DTA_LOW<7> 66 RAM_A2 17 CAR_DTA_HIGH<0> 67 OE_RAM_UPPER 18 CAR_DTA_HIGH<1> 68 RAM_A3 19 CAR_DTA_HIGH<2> 69 GND 20 CAR_DTA_HIGH<3> 70 RAM_A11 21 GND 71 RAM_A4 22 CAR_DTA_HIGH<4> 72 RAM_A9 23 CAR_DTA_HIGH<5> 73 RAM_A5 24 CAR_DTA_HIGH<6> 74 RAM_A8 25 CAR_DTA_HIGH<7> 75 GND 26 VCC 76 RAM_A6 27 R_W_LED 77 RAM_A13 28 RAM_UP_LED 78 RAM_A7 29 RAM_LOW_LED 79 RAM_A12 30 KPR 80 RAM_A14 31 GND 81 RAM_A15 32 KPR 82 KPR 33 TRIG_WE_OUT 83 TDO 34 KPR 84 GND 35 DTA_LOW_RAM<3> 85 KPR 36 DTA_LOW_RAM<4> 86 LDS 37 DTA_LOW_RAM<5> 87 UDS 38 VCC 88 VCC 39 DTA_LOW_RAM<2> 89 CART_A1 40 DTA_LOW_RAM<6> 90 CART_ROM4 41 DTA_LOW_RAM<1> 91 CART_A2 42 DTA_LOW_RAM<7> 92 CART_ROM3 43 DTA_LOW_RAM<0> 93 CART_A3 44 GND 94 CART_ADDR<3> 45 TDI 95 CART_A4 46 KPR 96 CART_A5 47 TMS 97 CART_ADDR<4> 48 TCK 98 VCC 49 negCE1_RAM_LOWER 99 CART_A6 50 OE_RAM_LOWER 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25