********** Mapped Logic ********** |
$OpTx$$OpTx$FX_DC$67_INV$100 <= (CART_ROM3 AND CART_ROM4); |
$OpTx$FX_DC$76 <= ((CART_ADDR(3) AND CART_ADDR(2) AND CART_ADDR(1) AND
CART_ADDR(0) AND NOT CART_ADDR(5) AND NOT CART_ADDR(4)) OR (CART_ADDR(3) AND NOT CART_ADDR(2) AND NOT CART_ADDR(1) AND CART_ADDR(0) AND CART_ADDR(5) AND NOT CART_ADDR(4)) OR (NOT CART_ADDR(3) AND CART_ADDR(2) AND NOT CART_ADDR(1) AND NOT CART_ADDR(0) AND CART_ADDR(5) AND CART_ADDR(4)) OR (NOT CART_ADDR(3) AND NOT CART_ADDR(2) AND CART_ADDR(1) AND NOT CART_ADDR(0) AND CART_ADDR(5) AND CART_ADDR(4))); |
CAR_DTA_HIGH_I(0) <= DTA_UP_RAM(0).PIN;
CAR_DTA_HIGH(0) <= CAR_DTA_HIGH_I(0) when CAR_DTA_HIGH_OE(0) = '1' else 'Z'; CAR_DTA_HIGH_OE(0) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_HIGH_I(1) <= DTA_UP_RAM(1).PIN;
CAR_DTA_HIGH(1) <= CAR_DTA_HIGH_I(1) when CAR_DTA_HIGH_OE(1) = '1' else 'Z'; CAR_DTA_HIGH_OE(1) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_HIGH_I(2) <= DTA_UP_RAM(2).PIN;
CAR_DTA_HIGH(2) <= CAR_DTA_HIGH_I(2) when CAR_DTA_HIGH_OE(2) = '1' else 'Z'; CAR_DTA_HIGH_OE(2) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_HIGH_I(3) <= DTA_UP_RAM(3).PIN;
CAR_DTA_HIGH(3) <= CAR_DTA_HIGH_I(3) when CAR_DTA_HIGH_OE(3) = '1' else 'Z'; CAR_DTA_HIGH_OE(3) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_HIGH_I(4) <= DTA_UP_RAM(4).PIN;
CAR_DTA_HIGH(4) <= CAR_DTA_HIGH_I(4) when CAR_DTA_HIGH_OE(4) = '1' else 'Z'; CAR_DTA_HIGH_OE(4) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_HIGH_I(5) <= DTA_UP_RAM(5).PIN;
CAR_DTA_HIGH(5) <= CAR_DTA_HIGH_I(5) when CAR_DTA_HIGH_OE(5) = '1' else 'Z'; CAR_DTA_HIGH_OE(5) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_HIGH_I(6) <= DTA_UP_RAM(6).PIN;
CAR_DTA_HIGH(6) <= CAR_DTA_HIGH_I(6) when CAR_DTA_HIGH_OE(6) = '1' else 'Z'; CAR_DTA_HIGH_OE(6) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_HIGH_I(7) <= DTA_UP_RAM(7).PIN;
CAR_DTA_HIGH(7) <= CAR_DTA_HIGH_I(7) when CAR_DTA_HIGH_OE(7) = '1' else 'Z'; CAR_DTA_HIGH_OE(7) <= (NOT UDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(0) <= DTA_LOW_RAM(0).PIN;
CAR_DTA_LOW(0) <= CAR_DTA_LOW_I(0) when CAR_DTA_LOW_OE(0) = '1' else 'Z'; CAR_DTA_LOW_OE(0) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(1) <= DTA_LOW_RAM(1).PIN;
CAR_DTA_LOW(1) <= CAR_DTA_LOW_I(1) when CAR_DTA_LOW_OE(1) = '1' else 'Z'; CAR_DTA_LOW_OE(1) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(2) <= DTA_LOW_RAM(2).PIN;
CAR_DTA_LOW(2) <= CAR_DTA_LOW_I(2) when CAR_DTA_LOW_OE(2) = '1' else 'Z'; CAR_DTA_LOW_OE(2) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(3) <= DTA_LOW_RAM(3).PIN;
CAR_DTA_LOW(3) <= CAR_DTA_LOW_I(3) when CAR_DTA_LOW_OE(3) = '1' else 'Z'; CAR_DTA_LOW_OE(3) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(4) <= DTA_LOW_RAM(4).PIN;
CAR_DTA_LOW(4) <= CAR_DTA_LOW_I(4) when CAR_DTA_LOW_OE(4) = '1' else 'Z'; CAR_DTA_LOW_OE(4) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(5) <= DTA_LOW_RAM(5).PIN;
CAR_DTA_LOW(5) <= CAR_DTA_LOW_I(5) when CAR_DTA_LOW_OE(5) = '1' else 'Z'; CAR_DTA_LOW_OE(5) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(6) <= DTA_LOW_RAM(6).PIN;
CAR_DTA_LOW(6) <= CAR_DTA_LOW_I(6) when CAR_DTA_LOW_OE(6) = '1' else 'Z'; CAR_DTA_LOW_OE(6) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
CAR_DTA_LOW_I(7) <= DTA_LOW_RAM(7).PIN;
CAR_DTA_LOW(7) <= CAR_DTA_LOW_I(7) when CAR_DTA_LOW_OE(7) = '1' else 'Z'; CAR_DTA_LOW_OE(7) <= (NOT LDS AND NOT OE_RAM_LOWER AND NOT $OpTx$$OpTx$FX_DC$67_INV$100); |
FTCPE_CODE_RST2: FTCPE port map (CODE_RST(2),'1',NOT XLXI_203/Q(1),XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF,'0'); |
DTA_LOW_RAM_I(0) <= CART_ADDR(0);
DTA_LOW_RAM(0) <= DTA_LOW_RAM_I(0) when DTA_LOW_RAM_OE(0) = '1' else 'Z'; DTA_LOW_RAM_OE(0) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_LOW_RAM_I(1) <= CART_ADDR(1);
DTA_LOW_RAM(1) <= DTA_LOW_RAM_I(1) when DTA_LOW_RAM_OE(1) = '1' else 'Z'; DTA_LOW_RAM_OE(1) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_LOW_RAM_I(2) <= CART_ADDR(2);
DTA_LOW_RAM(2) <= DTA_LOW_RAM_I(2) when DTA_LOW_RAM_OE(2) = '1' else 'Z'; DTA_LOW_RAM_OE(2) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_LOW_RAM_I(3) <= CART_ADDR(3);
DTA_LOW_RAM(3) <= DTA_LOW_RAM_I(3) when DTA_LOW_RAM_OE(3) = '1' else 'Z'; DTA_LOW_RAM_OE(3) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_LOW_RAM_I(4) <= CART_ADDR(4);
DTA_LOW_RAM(4) <= DTA_LOW_RAM_I(4) when DTA_LOW_RAM_OE(4) = '1' else 'Z'; DTA_LOW_RAM_OE(4) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_LOW_RAM_I(5) <= CART_ADDR(5);
DTA_LOW_RAM(5) <= DTA_LOW_RAM_I(5) when DTA_LOW_RAM_OE(5) = '1' else 'Z'; DTA_LOW_RAM_OE(5) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_LOW_RAM_I(6) <= CART_ADDR(6);
DTA_LOW_RAM(6) <= DTA_LOW_RAM_I(6) when DTA_LOW_RAM_OE(6) = '1' else 'Z'; DTA_LOW_RAM_OE(6) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_LOW_RAM_I(7) <= CART_ADDR(7);
DTA_LOW_RAM(7) <= DTA_LOW_RAM_I(7) when DTA_LOW_RAM_OE(7) = '1' else 'Z'; DTA_LOW_RAM_OE(7) <= (NOT CART_ROM3 AND NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(0) <= CART_ADDR(0);
DTA_UP_RAM(0) <= DTA_UP_RAM_I(0) when DTA_UP_RAM_OE(0) = '1' else 'Z'; DTA_UP_RAM_OE(0) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(1) <= CART_ADDR(1);
DTA_UP_RAM(1) <= DTA_UP_RAM_I(1) when DTA_UP_RAM_OE(1) = '1' else 'Z'; DTA_UP_RAM_OE(1) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(2) <= CART_ADDR(2);
DTA_UP_RAM(2) <= DTA_UP_RAM_I(2) when DTA_UP_RAM_OE(2) = '1' else 'Z'; DTA_UP_RAM_OE(2) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(3) <= CART_ADDR(3);
DTA_UP_RAM(3) <= DTA_UP_RAM_I(3) when DTA_UP_RAM_OE(3) = '1' else 'Z'; DTA_UP_RAM_OE(3) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(4) <= CART_ADDR(4);
DTA_UP_RAM(4) <= DTA_UP_RAM_I(4) when DTA_UP_RAM_OE(4) = '1' else 'Z'; DTA_UP_RAM_OE(4) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(5) <= CART_ADDR(5);
DTA_UP_RAM(5) <= DTA_UP_RAM_I(5) when DTA_UP_RAM_OE(5) = '1' else 'Z'; DTA_UP_RAM_OE(5) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(6) <= CART_ADDR(6);
DTA_UP_RAM(6) <= DTA_UP_RAM_I(6) when DTA_UP_RAM_OE(6) = '1' else 'Z'; DTA_UP_RAM_OE(6) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
DTA_UP_RAM_I(7) <= CART_ADDR(7);
DTA_UP_RAM(7) <= DTA_UP_RAM_I(7) when DTA_UP_RAM_OE(7) = '1' else 'Z'; DTA_UP_RAM_OE(7) <= (NOT CART_ROM3 AND RAM_LOWER_LED AND OE_RAM_LOWER); |
FDCPE_OE_RAM_LOWER: FDCPE port map (OE_RAM_LOWER,'1',OE_RAM_LOWER_C,OE_RAM_LOWER_CLR,'0');
OE_RAM_LOWER_C <= (CART_A4 AND NOT CART_ROM4 AND WR_GO); OE_RAM_LOWER_CLR <= (NOT CART_ROM4 AND CART_A3); |
FDCPE_OE_RAM_UPPER: FDCPE port map (OE_RAM_UPPER,'1',OE_RAM_UPPER_C,OE_RAM_UPPER_CLR,'0');
OE_RAM_UPPER_C <= (CART_A4 AND NOT CART_ROM4 AND WR_GO); OE_RAM_UPPER_CLR <= (NOT CART_ROM4 AND CART_A3); |
RAM_A0 <= ((adres(0) AND OE_RAM_LOWER)
OR (CART_A1 AND NOT OE_RAM_LOWER)); |
RAM_A1 <= ((adres(1) AND OE_RAM_LOWER)
OR (CART_A2 AND NOT OE_RAM_LOWER)); |
RAM_A10 <= ((adres(10) AND OE_RAM_LOWER)
OR (CART_ADDR(3) AND NOT OE_RAM_LOWER)); |
RAM_A11 <= ((adres(11) AND OE_RAM_LOWER)
OR (CART_ADDR(4) AND NOT OE_RAM_LOWER)); |
RAM_A12 <= ((adres(12) AND OE_RAM_LOWER)
OR (CART_ADDR(5) AND NOT OE_RAM_LOWER)); |
RAM_A13 <= ((adres(13) AND OE_RAM_LOWER)
OR (CART_ADDR(6) AND NOT OE_RAM_LOWER)); |
RAM_A14 <= ((adres(14) AND OE_RAM_LOWER)
OR (CART_ADDR(7) AND NOT OE_RAM_LOWER)); |
RAM_A15 <= ((adres(15) AND OE_RAM_LOWER)
OR (CART_ROM4 AND NOT OE_RAM_LOWER)); |
RAM_A2 <= ((adres(2) AND OE_RAM_LOWER)
OR (CART_A3 AND NOT OE_RAM_LOWER)); |
RAM_A3 <= ((adres(3) AND OE_RAM_LOWER)
OR (CART_A4 AND NOT OE_RAM_LOWER)); |
RAM_A4 <= ((adres(4) AND OE_RAM_LOWER)
OR (CART_A5 AND NOT OE_RAM_LOWER)); |
RAM_A5 <= ((adres(5) AND OE_RAM_LOWER)
OR (CART_A6 AND NOT OE_RAM_LOWER)); |
RAM_A6 <= ((adres(6) AND OE_RAM_LOWER)
OR (CART_A7 AND NOT OE_RAM_LOWER)); |
RAM_A7 <= ((adres(7) AND OE_RAM_LOWER)
OR (CART_ADDR(0) AND NOT OE_RAM_LOWER)); |
RAM_A8 <= ((adres(8) AND OE_RAM_LOWER)
OR (CART_ADDR(1) AND NOT OE_RAM_LOWER)); |
RAM_A9 <= ((adres(9) AND OE_RAM_LOWER)
OR (CART_ADDR(2) AND NOT OE_RAM_LOWER)); |
FDCPE_RAM_LOWER_LED: FDCPE port map (RAM_LOWER_LED,'1',RAM_LOWER_LED_C,RAM_LOWER_LED_CLR,'0');
RAM_LOWER_LED_C <= (NOT CART_ROM4 AND CART_A2); RAM_LOWER_LED_CLR <= (NOT CART_ROM4 AND CART_A1); |
RAM_LOW_LED <= NOT ((NOT RAM_LOWER_LED AND OE_RAM_LOWER)); |
RAM_UP_LED <= NOT ((RAM_LOWER_LED AND OE_RAM_LOWER)); |
R_W_LED <= NOT ((NOT adres(8) AND OE_RAM_LOWER)); |
TRIG_WE_OUT <= (NOT CART_ROM3 AND XLXN_477 AND OE_RAM_LOWER); |
FDCPE_WR_GO: FDCPE port map (WR_GO,'1',XLXN_418,WR_GO_CLR,'0');
WR_GO_CLR <= (NOT CART_ROM4 AND CART_A3); |
FTCPE_XLXI_203/Q0: FTCPE port map (XLXI_203/Q(0),'1',XLXI_203/Q_C(0),XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF,'0');
XLXI_203/Q_C(0) <= (NOT CART_ADDR(7) AND CART_ADDR(6) AND NOT CART_ROM4 AND $OpTx$FX_DC$76); |
XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF <= ((WR_GO)
OR (NOT CART_ROM4 AND CART_A3)); |
FTCPE_XLXI_203/Q1: FTCPE port map (XLXI_203/Q(1),'1',NOT XLXI_203/Q(0),XLXI_203/Q(1)/XLXI_203/Q(1)_RSTF,'0'); |
FDCPE_XLXN_237: FDCPE port map (XLXN_237,'1',XLXN_237_C,CODE_RST(2),'0');
XLXN_237_C <= (NOT CART_ADDR(3) AND CART_ADDR(2) AND NOT CART_ADDR(1) AND NOT CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND CART_ADDR(5) AND CART_ADDR(4) AND NOT CART_ROM4); |
FDCPE_XLXN_238: FDCPE port map (XLXN_238,XLXN_237,XLXN_238_C,CODE_RST(2),'0');
XLXN_238_C <= (CART_ADDR(3) AND CART_ADDR(2) AND CART_ADDR(1) AND CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND NOT CART_ADDR(5) AND NOT CART_ADDR(4) AND NOT CART_ROM4); |
FDCPE_XLXN_239: FDCPE port map (XLXN_239,XLXN_238,XLXN_239_C,CODE_RST(2),'0');
XLXN_239_C <= (NOT CART_ADDR(3) AND NOT CART_ADDR(2) AND CART_ADDR(1) AND NOT CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND CART_ADDR(5) AND CART_ADDR(4) AND NOT CART_ROM4); |
FDCPE_XLXN_418: FDCPE port map (XLXN_418,XLXN_239,XLXN_418_C,CODE_RST(2),'0');
XLXN_418_C <= (CART_ADDR(3) AND NOT CART_ADDR(2) AND NOT CART_ADDR(1) AND CART_ADDR(0) AND NOT CART_ADDR(7) AND CART_ADDR(6) AND CART_ADDR(5) AND NOT CART_ADDR(4) AND NOT CART_ROM4); |
FDCPE_XLXN_477: FDCPE port map (XLXN_477,'1',XLXN_477_C,XLXN_477_CLR,'0');
XLXN_477_C <= (NOT CART_ROM4 AND CART_A5 AND OE_RAM_LOWER); XLXN_477_CLR <= (NOT CART_ROM4 AND CART_A6 AND OE_RAM_LOWER); |
FTCPE_adres0: FTCPE port map (adres(0),'1',adres_C(0),adres_CLR(0),'0',OE_RAM_LOWER);
adres_C(0) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(0) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres1: FTCPE port map (adres(1),adres(0),adres_C(1),adres_CLR(1),'0',OE_RAM_LOWER);
adres_C(1) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(1) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres2: FTCPE port map (adres(2),adres_T(2),adres_C(2),adres_CLR(2),'0',OE_RAM_LOWER);
adres_T(2) <= (adres(0) AND adres(1)); adres_C(2) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(2) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres3: FTCPE port map (adres(3),adres_T(3),adres_C(3),adres_CLR(3),'0',OE_RAM_LOWER);
adres_T(3) <= (adres(0) AND adres(1) AND adres(2)); adres_C(3) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(3) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres4: FTCPE port map (adres(4),adres_T(4),adres_C(4),adres_CLR(4),'0',OE_RAM_LOWER);
adres_T(4) <= (adres(0) AND adres(1) AND adres(2) AND adres(3)); adres_C(4) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(4) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres5: FTCPE port map (adres(5),adres_T(5),adres_C(5),adres_CLR(5),'0',OE_RAM_LOWER);
adres_T(5) <= (adres(0) AND adres(4) AND adres(1) AND adres(2) AND adres(3)); adres_C(5) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(5) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres6: FTCPE port map (adres(6),adres_T(6),adres_C(6),adres_CLR(6),'0',OE_RAM_LOWER);
adres_T(6) <= (adres(0) AND adres(4) AND adres(1) AND adres(5) AND adres(2) AND adres(3)); adres_C(6) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(6) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres7: FTCPE port map (adres(7),adres_T(7),adres_C(7),adres_CLR(7),'0',OE_RAM_LOWER);
adres_T(7) <= (adres(0) AND adres(4) AND adres(1) AND adres(5) AND adres(2) AND adres(6) AND adres(3)); adres_C(7) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(7) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres8: FTCPE port map (adres(8),adres_T(8),adres_C(8),adres_CLR(8),'0',OE_RAM_LOWER);
adres_T(8) <= (adres(0) AND adres(4) AND adres(1) AND adres(5) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(8) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(8) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres9: FTCPE port map (adres(9),adres_T(9),adres_C(9),adres_CLR(9),'0',OE_RAM_LOWER);
adres_T(9) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(9) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(9) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres10: FTCPE port map (adres(10),adres_T(10),adres_C(10),adres_CLR(10),'0',OE_RAM_LOWER);
adres_T(10) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(9) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(10) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(10) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres11: FTCPE port map (adres(11),adres_T(11),adres_C(11),adres_CLR(11),'0',OE_RAM_LOWER);
adres_T(11) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(2) AND adres(6) AND adres(3) AND adres(7)); adres_C(11) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(11) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres12: FTCPE port map (adres(12),adres_T(12),adres_C(12),adres_CLR(12),'0',OE_RAM_LOWER);
adres_T(12) <= (adres(0) AND adres(4) AND adres(8) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(2) AND adres(6) AND adres(11) AND adres(3) AND adres(7)); adres_C(12) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(12) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres13: FTCPE port map (adres(13),adres_T(13),adres_C(13),adres_CLR(13),'0',OE_RAM_LOWER);
adres_T(13) <= (adres(0) AND adres(4) AND adres(8) AND adres(12) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(2) AND adres(6) AND adres(11) AND adres(3) AND adres(7)); adres_C(13) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(13) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres14: FTCPE port map (adres(14),adres_T(14),adres_C(14),adres_CLR(14),'0',OE_RAM_LOWER);
adres_T(14) <= (adres(0) AND adres(4) AND adres(8) AND adres(12) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(13) AND adres(2) AND adres(6) AND adres(11) AND adres(3) AND adres(7)); adres_C(14) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(14) <= (NOT CART_ROM4 AND CART_A7); |
FTCPE_adres15: FTCPE port map (adres(15),adres_T(15),adres_C(15),adres_CLR(15),'0',OE_RAM_LOWER);
adres_T(15) <= (adres(0) AND adres(4) AND adres(8) AND adres(12) AND adres(1) AND adres(5) AND adres(9) AND adres(10) AND adres(13) AND adres(2) AND adres(6) AND adres(11) AND adres(14) AND adres(3) AND adres(7)); adres_C(15) <= NOT ((NOT CART_ROM3 AND OE_RAM_LOWER)); adres_CLR(15) <= (NOT CART_ROM4 AND CART_A7); |
negCE1_RAM_LOWER <= (RAM_LOWER_LED AND OE_RAM_LOWER); |
negCE1_RAM_UPPER <= (NOT RAM_LOWER_LED AND OE_RAM_LOWER); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |