cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: TIGARI_CTRL Date: 8-19-2020, 10:00PM Device Used: XC9572XL-10-VQ64 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 37 /72 ( 51%) 65 /360 ( 18%) 46 /216 ( 21%) 21 /72 ( 29%) 48 /52 ( 92%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 8/18 13/54 17/90 10/13 FB2 8/18 6/54 10/90 13/13* FB3 13/18 14/54 18/90 14/14* FB4 8/18 13/54 20/90 11/12 ----- ----- ----- ----- 37/72 46/216 65/360 48/52 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 16 16 | I/O : 43 46 Output : 24 24 | GCK/IO : 2 3 Bidirectional : 8 8 | GTS/IO : 2 2 GCK : 0 0 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 48 48 ** Power Data ** There are 37 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'TIGARI_CTRL.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'CS_SELECT_IN' based upon the LOC constraint 'P16'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'CS_SELECT_IN_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 32 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State DATA_INTERNAL<4> 2 4 FB1_10 18 I/O O STD FAST RESET DATA_INTERNAL<2> 2 4 FB1_12 23 I/O O STD FAST RESET DATA_INTERNAL<5> 2 4 FB1_14 17 GCK/I/O O STD FAST RESET DATA_INTERNAL<6> 2 4 FB1_15 19 I/O O STD FAST RESET DATA_INTERNAL<7> 2 4 FB1_17 20 I/O O STD FAST RESET ATARI_DATA<7> 2 5 FB2_2 60 I/O I/O STD FAST ATARI_DATA<6> 2 5 FB2_4 59 I/O I/O STD FAST ATARI_DATA<0> 1 4 FB2_5 61 I/O I/O STD FAST ATARI_DATA<3> 1 4 FB2_6 62 I/O I/O STD FAST ATARI_DATA<1> 1 4 FB2_8 63 I/O I/O STD FAST ATARI_DATA<2> 1 4 FB2_9 64 GSR/I/O I/O STD FAST ATARI_DATA<5> 1 4 FB2_10 1 I/O I/O STD FAST ATARI_DATA<4> 1 4 FB2_11 2 GTS/I/O I/O STD FAST DATA_INTERNAL<3> 2 4 FB3_2 22 I/O O STD FAST RESET D520 1 4 FB3_3 31 I/O O STD FAST D540 1 4 FB3_4 32 I/O O STD FAST DATA_INTERNAL<1> 2 4 FB3_5 24 I/O O STD FAST RESET D580 1 4 FB3_6 34 I/O O STD FAST DATA_INTERNAL<0> 2 4 FB3_8 25 I/O O STD FAST RESET D500 1 4 FB3_9 27 I/O O STD FAST CE_WE_IC2 2 5 FB3_10 39 I/O O STD FAST SET D560 1 4 FB3_11 33 I/O O STD FAST D5A0 1 4 FB3_14 35 I/O O STD FAST D5C0 1 4 FB3_15 36 I/O O STD FAST CE_WE_IC1 2 5 FB3_16 42 I/O O STD FAST SET D5E0 1 4 FB3_17 38 I/O O STD FAST AUDCTL2 3 6 FB4_3 46 I/O O STD FAST RESET NEG_AUDCTL1 3 6 FB4_4 47 I/O O STD FAST SET GEN_OUT_4 2 2 FB4_6 49 I/O O STD FAST RESET NEG_AUDCTL2 3 6 FB4_8 45 I/O O STD FAST SET OUT_HELPER1 2 3 FB4_10 51 I/O O STD FAST RESET AUDCTL1 3 6 FB4_11 48 I/O O STD FAST RESET ** 5 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State XLXN_96 2 2 FB1_13 STD RESET XLXN_37 2 2 FB1_16 STD RESET XLXN_92 3 5 FB1_18 STD RESET XLXI_99/Q0 1 1 FB4_17 STD RESET XLXN_104 3 5 FB4_18 STD RESET ** 16 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use Atari_A5 FB1_2 8 I/O I Atari_A2 FB1_5 9 I/O I Atari_A4 FB1_6 10 I/O I Atari_A3 FB1_8 11 I/O I CS_SELECT_IN FB1_11 16 GCK/I/O I Atari_RW FB2_3 58 I/O I Atari_A7 FB2_12 4 I/O I Atari_A0 FB2_14 5 GTS/I/O I Atari_A6 FB2_15 6 I/O I Atari_A1 FB2_17 7 I/O I Ready_2 FB3_12 40 I/O I Ready_1 FB4_2 43 I/O I MUTED FB4_5 44 I/O I GEN_IN FB4_14 50 I/O I Atari_CCTL FB4_15 56 I/O I Atari_PHI2 FB4_17 57 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 8 I/O I (unused) 0 0 0 5 FB1_3 12 I/O (unused) 0 0 0 5 FB1_4 13 I/O (unused) 0 0 0 5 FB1_5 9 I/O I (unused) 0 0 0 5 FB1_6 10 I/O I (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 11 I/O I (unused) 0 0 0 5 FB1_9 15 GCK/I/O DATA_INTERNAL<4> 2 0 0 3 FB1_10 18 I/O O (unused) 0 0 0 5 FB1_11 16 GCK/I/O I DATA_INTERNAL<2> 2 0 0 3 FB1_12 23 I/O O XLXN_96 2 0 0 3 FB1_13 (b) (b) DATA_INTERNAL<5> 2 0 0 3 FB1_14 17 GCK/I/O O DATA_INTERNAL<6> 2 0 0 3 FB1_15 19 I/O O XLXN_37 2 0 0 3 FB1_16 (b) (b) DATA_INTERNAL<7> 2 0 0 3 FB1_17 20 I/O O XLXN_92 3 0 0 2 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: Atari_A0 6: ATARI_DATA<2>.PIN 10: Ready_1 2: Atari_PHI2 7: ATARI_DATA<6>.PIN 11: Ready_2 3: Atari_RW 8: ATARI_DATA<5>.PIN 12: XLXN_37 4: CS_SELECT_IN 9: ATARI_DATA<4>.PIN 13: XLXN_96 5: ATARI_DATA<7>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DATA_INTERNAL<4> .XXX....X............................... 4 DATA_INTERNAL<2> .XXX.X.................................. 4 XLXN_96 ..........X.X........................... 2 DATA_INTERNAL<5> .XXX...X................................ 4 DATA_INTERNAL<6> .XXX..X................................. 4 XLXN_37 .........X.X............................ 2 DATA_INTERNAL<7> .XXXX................................... 4 XLXN_92 XXXX.......X............................ 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 6/48 Number of signals used by logic mapping into function block: 6 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) ATARI_DATA<7> 2 0 0 3 FB2_2 60 I/O I/O (unused) 0 0 0 5 FB2_3 58 I/O I ATARI_DATA<6> 2 0 0 3 FB2_4 59 I/O I/O ATARI_DATA<0> 1 0 0 4 FB2_5 61 I/O I/O ATARI_DATA<3> 1 0 0 4 FB2_6 62 I/O I/O (unused) 0 0 0 5 FB2_7 (b) ATARI_DATA<1> 1 0 0 4 FB2_8 63 I/O I/O ATARI_DATA<2> 1 0 0 4 FB2_9 64 GSR/I/O I/O ATARI_DATA<5> 1 0 0 4 FB2_10 1 I/O I/O ATARI_DATA<4> 1 0 0 4 FB2_11 2 GTS/I/O I/O (unused) 0 0 0 5 FB2_12 4 I/O I (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 5 GTS/I/O I (unused) 0 0 0 5 FB2_15 6 I/O I (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 0 5 FB2_17 7 I/O I (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: Atari_A2 3: Atari_RW 5: Ready_1 2: Atari_PHI2 4: CS_SELECT_IN 6: Ready_2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ATARI_DATA<7> XXXXX................................... 5 ATARI_DATA<6> XXXX.X.................................. 5 ATARI_DATA<0> XXXX.................................... 4 ATARI_DATA<3> XXXX.................................... 4 ATARI_DATA<1> XXXX.................................... 4 ATARI_DATA<2> XXXX.................................... 4 ATARI_DATA<5> XXXX.................................... 4 ATARI_DATA<4> XXXX.................................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 14/40 Number of signals used by logic mapping into function block: 14 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) DATA_INTERNAL<3> 2 0 0 3 FB3_2 22 I/O O D520 1 0 0 4 FB3_3 31 I/O O D540 1 0 0 4 FB3_4 32 I/O O DATA_INTERNAL<1> 2 0 0 3 FB3_5 24 I/O O D580 1 0 0 4 FB3_6 34 I/O O (unused) 0 0 0 5 FB3_7 (b) DATA_INTERNAL<0> 2 0 0 3 FB3_8 25 I/O O D500 1 0 0 4 FB3_9 27 I/O O CE_WE_IC2 2 0 0 3 FB3_10 39 I/O O D560 1 0 0 4 FB3_11 33 I/O O (unused) 0 0 0 5 FB3_12 40 I/O I (unused) 0 0 0 5 FB3_13 (b) D5A0 1 0 0 4 FB3_14 35 I/O O D5C0 1 0 0 4 FB3_15 36 I/O O CE_WE_IC1 2 0 0 3 FB3_16 42 I/O O D5E0 1 0 0 4 FB3_17 38 I/O O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: Atari_A5 6: Atari_RW 11: XLXN_104 2: Atari_A6 7: CS_SELECT_IN 12: XLXN_37 3: Atari_A7 8: ATARI_DATA<1>.PIN 13: XLXN_92 4: Atari_CCTL 9: ATARI_DATA<0>.PIN 14: XLXN_96 5: Atari_PHI2 10: ATARI_DATA<3>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs DATA_INTERNAL<3> ....XXX..X.............................. 4 D520 XXXX.................................... 4 D540 XXXX.................................... 4 DATA_INTERNAL<1> ....XXXX................................ 4 D580 XXXX.................................... 4 DATA_INTERNAL<0> ....XXX.X............................... 4 D500 XXXX.................................... 4 CE_WE_IC2 ....XXX...X..X.......................... 5 D560 XXXX.................................... 4 D5A0 XXXX.................................... 4 D5C0 XXXX.................................... 4 CE_WE_IC1 ....XXX....XX........................... 5 D5E0 XXXX.................................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 43 I/O I AUDCTL2 3 0 0 2 FB4_3 46 I/O O NEG_AUDCTL1 3 0 0 2 FB4_4 47 I/O O (unused) 0 0 0 5 FB4_5 44 I/O I GEN_OUT_4 2 0 0 3 FB4_6 49 I/O O (unused) 0 0 0 5 FB4_7 (b) NEG_AUDCTL2 3 0 0 2 FB4_8 45 I/O O (unused) 0 0 0 5 FB4_9 (b) OUT_HELPER1 2 0 0 3 FB4_10 51 I/O O AUDCTL1 3 0 0 2 FB4_11 48 I/O O (unused) 0 0 0 5 FB4_12 52 I/O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 50 I/O I (unused) 0 0 0 5 FB4_15 56 I/O I (unused) 0 0 0 5 FB4_16 (b) XLXI_99/Q0 1 0 0 4 FB4_17 57 I/O I XLXN_104 3 0 0 2 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: AUDCTL1 6: Atari_PHI2 10: GEN_OUT_4 2: AUDCTL2 7: Atari_RW 11: MUTED 3: Atari_A1 8: CS_SELECT_IN 12: XLXI_99/Q0 4: Atari_A3 9: GEN_IN 13: XLXN_96 5: Atari_A4 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs AUDCTL2 .X..XXXX..X............................. 6 NEG_AUDCTL1 X..X.XXX..X............................. 6 GEN_OUT_4 ........X..X............................ 2 NEG_AUDCTL2 .X..XXXX..X............................. 6 OUT_HELPER1 ........XX.X............................ 3 AUDCTL1 X..X.XXX..X............................. 6 XLXI_99/Q0 ........X............................... 1 XLXN_104 ..X..XXX....X........................... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** ATARI_DATA_I(0) <= '0'; ATARI_DATA(0) <= ATARI_DATA_I(0) when ATARI_DATA_OE(0) = '1' else 'Z'; ATARI_DATA_OE(0) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); ATARI_DATA_I(1) <= '0'; ATARI_DATA(1) <= ATARI_DATA_I(1) when ATARI_DATA_OE(1) = '1' else 'Z'; ATARI_DATA_OE(1) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); ATARI_DATA_I(2) <= '1'; ATARI_DATA(2) <= ATARI_DATA_I(2) when ATARI_DATA_OE(2) = '1' else 'Z'; ATARI_DATA_OE(2) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); ATARI_DATA_I(3) <= '0'; ATARI_DATA(3) <= ATARI_DATA_I(3) when ATARI_DATA_OE(3) = '1' else 'Z'; ATARI_DATA_OE(3) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); ATARI_DATA_I(4) <= '1'; ATARI_DATA(4) <= ATARI_DATA_I(4) when ATARI_DATA_OE(4) = '1' else 'Z'; ATARI_DATA_OE(4) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); ATARI_DATA_I(5) <= '0'; ATARI_DATA(5) <= ATARI_DATA_I(5) when ATARI_DATA_OE(5) = '1' else 'Z'; ATARI_DATA_OE(5) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); ATARI_DATA_I(6) <= Ready_2; ATARI_DATA(6) <= ATARI_DATA_I(6) when ATARI_DATA_OE(6) = '1' else 'Z'; ATARI_DATA_OE(6) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); ATARI_DATA_I(7) <= Ready_1; ATARI_DATA(7) <= ATARI_DATA_I(7) when ATARI_DATA_OE(7) = '1' else 'Z'; ATARI_DATA_OE(7) <= (NOT CS_SELECT_IN AND Atari_RW AND Atari_PHI2 AND Atari_A2); FDCPE_AUDCTL1: FDCPE port map (AUDCTL1,AUDCTL1_D,AUDCTL1_C,NOT MUTED,'0'); AUDCTL1_D <= (NOT Atari_A3 AND NOT AUDCTL1); AUDCTL1_C <= (NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2); FDCPE_AUDCTL2: FDCPE port map (AUDCTL2,AUDCTL2_D,AUDCTL2_C,NOT MUTED,'0'); AUDCTL2_D <= (NOT Atari_A4 AND NOT AUDCTL2); AUDCTL2_C <= (NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2); FDCPE_CE_WE_IC1: FDCPE port map (CE_WE_IC1,'0',CE_WE_IC1_C,'0',XLXN_37); CE_WE_IC1_C <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2 AND XLXN_92)); FDCPE_CE_WE_IC2: FDCPE port map (CE_WE_IC2,'0',CE_WE_IC2_C,'0',XLXN_96); CE_WE_IC2_C <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2 AND XLXN_104)); D500 <= NOT ((NOT Atari_A7 AND NOT Atari_A6 AND NOT Atari_A5 AND NOT Atari_CCTL)); D520 <= NOT ((NOT Atari_A7 AND NOT Atari_A6 AND Atari_A5 AND NOT Atari_CCTL)); D540 <= NOT ((NOT Atari_A7 AND Atari_A6 AND NOT Atari_A5 AND NOT Atari_CCTL)); D560 <= NOT ((NOT Atari_A7 AND Atari_A6 AND Atari_A5 AND NOT Atari_CCTL)); D580 <= NOT ((Atari_A7 AND NOT Atari_A6 AND NOT Atari_A5 AND NOT Atari_CCTL)); D5A0 <= NOT ((Atari_A7 AND NOT Atari_A6 AND Atari_A5 AND NOT Atari_CCTL)); D5C0 <= NOT ((Atari_A7 AND Atari_A6 AND NOT Atari_A5 AND NOT Atari_CCTL)); D5E0 <= NOT ((Atari_A7 AND Atari_A6 AND Atari_A5 AND NOT Atari_CCTL)); FDCPE_DATA_INTERNAL0: FDCPE port map (DATA_INTERNAL(0),ATARI_DATA(0).PIN,DATA_INTERNAL_C(0),'0','0'); DATA_INTERNAL_C(0) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FDCPE_DATA_INTERNAL1: FDCPE port map (DATA_INTERNAL(1),ATARI_DATA(1).PIN,DATA_INTERNAL_C(1),'0','0'); DATA_INTERNAL_C(1) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FDCPE_DATA_INTERNAL2: FDCPE port map (DATA_INTERNAL(2),ATARI_DATA(2).PIN,DATA_INTERNAL_C(2),'0','0'); DATA_INTERNAL_C(2) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FDCPE_DATA_INTERNAL3: FDCPE port map (DATA_INTERNAL(3),ATARI_DATA(3).PIN,DATA_INTERNAL_C(3),'0','0'); DATA_INTERNAL_C(3) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FDCPE_DATA_INTERNAL4: FDCPE port map (DATA_INTERNAL(4),ATARI_DATA(4).PIN,DATA_INTERNAL_C(4),'0','0'); DATA_INTERNAL_C(4) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FDCPE_DATA_INTERNAL5: FDCPE port map (DATA_INTERNAL(5),ATARI_DATA(5).PIN,DATA_INTERNAL_C(5),'0','0'); DATA_INTERNAL_C(5) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FDCPE_DATA_INTERNAL6: FDCPE port map (DATA_INTERNAL(6),ATARI_DATA(6).PIN,DATA_INTERNAL_C(6),'0','0'); DATA_INTERNAL_C(6) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FDCPE_DATA_INTERNAL7: FDCPE port map (DATA_INTERNAL(7),ATARI_DATA(7).PIN,DATA_INTERNAL_C(7),'0','0'); DATA_INTERNAL_C(7) <= NOT ((NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2)); FTCPE_GEN_OUT_4: FTCPE port map (GEN_OUT_4,XLXI_99/Q0,GEN_IN,'0','0'); FDCPE_NEG_AUDCTL1: FDCPE port map (NEG_AUDCTL1,NEG_AUDCTL1_D,NEG_AUDCTL1_C,'0',NOT MUTED); NEG_AUDCTL1_D <= (NOT Atari_A3 AND NOT AUDCTL1); NEG_AUDCTL1_C <= (NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2); FDCPE_NEG_AUDCTL2: FDCPE port map (NEG_AUDCTL2,NEG_AUDCTL2_D,NEG_AUDCTL2_C,'0',NOT MUTED); NEG_AUDCTL2_D <= (NOT Atari_A4 AND NOT AUDCTL2); NEG_AUDCTL2_C <= (NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2); FTCPE_OUT_HELPER1: FTCPE port map (OUT_HELPER1,OUT_HELPER1_T,GEN_IN,'0','0'); OUT_HELPER1_T <= (GEN_OUT_4 AND XLXI_99/Q0); FTCPE_XLXI_99/Q0: FTCPE port map (XLXI_99/Q0,'1',GEN_IN,'0','0'); FDCPE_XLXN_104: FDCPE port map (XLXN_104,Atari_A1,XLXN_104_C,XLXN_96,'0'); XLXN_104_C <= (NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2); FDCPE_XLXN_37: FDCPE port map (XLXN_37,'1',Ready_1,XLXN_37,'0'); FDCPE_XLXN_92: FDCPE port map (XLXN_92,Atari_A0,XLXN_92_C,XLXN_37,'0'); XLXN_92_C <= (NOT CS_SELECT_IN AND NOT Atari_RW AND Atari_PHI2); FDCPE_XLXN_96: FDCPE port map (XLXN_96,'1',Ready_2,XLXN_96,'0'); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-10-VQ64 ----------------------------------------------- /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \ | 49 32 | | 50 31 | | 51 30 | | 52 29 | | 53 28 | | 54 27 | | 55 26 | | 56 XC9572XL-10-VQ64 25 | | 57 24 | | 58 23 | | 59 22 | | 60 21 | | 61 20 | | 62 19 | | 63 18 | | 64 17 | \ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 / ----------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 ATARI_DATA<5> 33 D560 2 ATARI_DATA<4> 34 D580 3 VCC 35 D5A0 4 Atari_A7 36 D5C0 5 Atari_A0 37 VCC 6 Atari_A6 38 D5E0 7 Atari_A1 39 CE_WE_IC2 8 Atari_A5 40 Ready_2 9 Atari_A2 41 GND 10 Atari_A4 42 CE_WE_IC1 11 Atari_A3 43 Ready_1 12 KPR 44 MUTED 13 KPR 45 NEG_AUDCTL2 14 GND 46 AUDCTL2 15 KPR 47 NEG_AUDCTL1 16 CS_SELECT_IN 48 AUDCTL1 17 DATA_INTERNAL<5> 49 GEN_OUT_4 18 DATA_INTERNAL<4> 50 GEN_IN 19 DATA_INTERNAL<6> 51 OUT_HELPER1 20 DATA_INTERNAL<7> 52 KPR 21 GND 53 TDO 22 DATA_INTERNAL<3> 54 GND 23 DATA_INTERNAL<2> 55 VCC 24 DATA_INTERNAL<1> 56 Atari_CCTL 25 DATA_INTERNAL<0> 57 Atari_PHI2 26 VCC 58 Atari_RW 27 D500 59 ATARI_DATA<6> 28 TDI 60 ATARI_DATA<7> 29 TMS 61 ATARI_DATA<0> 30 TCK 62 ATARI_DATA<3> 31 D520 63 ATARI_DATA<1> 32 D540 64 ATARI_DATA<2> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-VQ64 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : OFF Global Set/Reset Optimization : OFF Global Ouput Enable Optimization : OFF Input Limit : 54 Pterm Limit : 25